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Subject: Re: [Qemu-devel] qemu-arm: wrong execution of post-indexed loads
	when	Rm and Rd are the same register
From: Lauro Ramos Venancio <lauro.venancio@indt.org.br>
In-Reply-To: <200703152204.41337.paul@codesourcery.com>
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Date: Fri, 16 Mar 2007 17:42:42 -0300
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I'm sending a new version of the patch that uses Base Restored data
abort model.

Lauro

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Content-Disposition: attachment; filename=00_ldr_writeback.patch
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diff -ru qemu-0.9.0.orig/target-arm/translate.c qemu-0.9.0/target-arm/translate.c
--- qemu-0.9.0.orig/target-arm/translate.c	2007-03-16 11:41:28.000000000 -0300
+++ qemu-0.9.0/target-arm/translate.c	2007-03-16 14:59:40.000000000 -0300
@@ -1556,7 +1556,6 @@
                         gen_ldst(ldsw, s);
                         break;
                     }
-                    gen_movl_reg_T0(s, rd);
                 } else if (sh & 2) {
                     /* doubleword */
                     if (sh & 1) {
@@ -1572,7 +1571,7 @@
                         gen_movl_reg_T0(s, rd);
                         gen_op_addl_T1_im(4);
                         gen_ldst(ldl, s);
-                        gen_movl_reg_T0(s, rd + 1);
+                        ++rd;
                     }
                     address_offset = -4;
                 } else {
@@ -1588,6 +1587,12 @@
                         gen_op_addl_T1_im(address_offset);
                     gen_movl_reg_T1(s, rn);
                 }
+
+                if ((insn & (1 << 20)) ||
+                    ((!(insn & (1 << 20)))&&((sh & 3) == 2))) {
+                    /* load */
+                    gen_movl_reg_T0(s, rd);
+                }
             }
             break;
         case 0x4:
@@ -1630,10 +1635,6 @@
                         gen_op_ldl_kernel();
                 }
 #endif
-                if (rd == 15)
-                    gen_bx(s);
-                else
-                    gen_movl_reg_T0(s, rd);
             } else {
                 /* store */
                 gen_movl_T0_reg(s, rd);
@@ -1662,6 +1663,13 @@
             } else if (insn & (1 << 21))
                 gen_movl_reg_T1(s, rn); {
             }
+            if (insn & (1 << 20)) {
+                /* load */
+                if (rd == 15)
+                    gen_bx(s);
+                else
+                    gen_movl_reg_T0(s, rd);
+            }
             break;
         case 0x08:
         case 0x09:
Only in qemu-0.9.0/target-arm: translate.c~

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