From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1HaHaR-00028c-Rm for qemu-devel@nongnu.org; Sat, 07 Apr 2007 16:32:39 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1HaHaQ-00028Q-5e for qemu-devel@nongnu.org; Sat, 07 Apr 2007 16:32:39 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1HaHaP-00028N-VT for qemu-devel@nongnu.org; Sat, 07 Apr 2007 16:32:38 -0400 Received: from bangui.magic.fr ([195.154.194.245]) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1HaHWm-0002wt-5p for qemu-devel@nongnu.org; Sat, 07 Apr 2007 16:28:52 -0400 Received: from [192.168.0.2] (ppp-36.net-723.magic.fr [80.118.184.36]) by bangui.magic.fr (8.13.1/8.13.1) with ESMTP id l37KSgnD008579 for ; Sat, 7 Apr 2007 22:28:44 +0200 Subject: Re: [Qemu-devel] qemu Makefile.target vl.h hw/acpi.c hw/adlib.c ... From: "J. Mayer" In-Reply-To: <200704072010.05798.paul@codesourcery.com> References: <1175970741.1516.5.camel@rapid> <200704072010.05798.paul@codesourcery.com> Content-Type: text/plain Date: Sat, 07 Apr 2007 22:28:46 +0200 Message-Id: <1175977726.1516.15.camel@rapid> Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Sat, 2007-04-07 at 20:10 +0100, Paul Brook wrote: > On Saturday 07 April 2007 19:32, J. Mayer wrote: > > On Sat, 2007-04-07 at 18:14 +0000, Paul Brook wrote: > > > CVSROOT: /sources/qemu > > > Module name: qemu > > > Changes by: Paul Brook 07/04/07 18:14:41 > > > > The patches in the PowerPC target seem complete nonsense. > > Can you give specific examples? I'm talking about the CPU code. There is NO notion of external IRQ allocation in the PowerPC specification. IRQ are completely out of the scope of the CPU emulation so the table of 32 void *IRQ pointers is the CPU structure is a complete nonsense. Where do you see in the PowerPC specification that those CPU have any notion of how the EXTERNAL IRQ controler works ? Where do you see that a machine with a PowerPC cannot manage more than 32 IRQ ? Where do you see ANY NOTION OF EXTERNAL IRQ MANAGEMENT in the PowerPC specification ? EXTERNAL IRQ MANAGEMENT IS NO WAY RELATED WITH CPU ! It's private to each IRQ controller. Saying anything else is just completely ignoring how real hardware works. SO your patch is a complete nonsense and YES IT BREAKS MY WORKS SO IT HAS TO BE REVERTED. If you don't, I'LL REVERT ALL POWERPC CODE AFFECTED BY THIS PATCH. > The CHRP code looks a bit broken, but no more so than before I started. > > > Furthermore, this kind of patch that break other guys work would likely > > to be discussed and not beeing imposed. > > It's been mentioned several times on this list (by Fabrice, specifically) that > this is the way to go. I did not received any single mail AT ALL saying "we're going to break your code, you can now throw away all the work you're doing". NOT ONE. So don't say "it's been discussed several times". > > I applied this now specifically because there are big ARM patches waiting to > be applied, and wanted to get this cleanup done before they went in. I don't contest you that you can do what is needed for ARM. JUST DON'T DO WEIRD THINGS IN CODE YOU SHOULD NOT MODIFY. J. Mayer Never organized