From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Ih0UO-0008Na-4W for qemu-devel@nongnu.org; Sun, 14 Oct 2007 06:14:28 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Ih0UN-0008Mu-Pf for qemu-devel@nongnu.org; Sun, 14 Oct 2007 06:14:27 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Ih0UN-0008Mi-Dj for qemu-devel@nongnu.org; Sun, 14 Oct 2007 06:14:27 -0400 Received: from bangui.magic.fr ([195.154.194.245]) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Ih0UM-0006kw-2O for qemu-devel@nongnu.org; Sun, 14 Oct 2007 06:14:26 -0400 Received: from [192.168.0.2] (ppp-36.net-123.static.magiconline.fr [80.118.184.36]) by bangui.magic.fr (8.13.1/8.13.1) with ESMTP id l9EAEL3V012387 for ; Sun, 14 Oct 2007 12:14:21 +0200 Subject: Re: [Qemu-devel] RFC: reverse-endian softmmu memory accessors From: "J. Mayer" In-Reply-To: References: <1192269372.9976.305.camel@rapid> <1192279414.9976.332.camel@rapid> <1192285067.9976.338.camel@rapid> <1192313247.9976.356.camel@rapid> Content-Type: text/plain Date: Sun, 14 Oct 2007 12:14:23 +0200 Message-Id: <1192356863.9976.374.camel@rapid> Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Sun, 2007-10-14 at 11:19 +0300, Blue Swirl wrote: > On 10/14/07, J. Mayer wrote: > > On Sat, 2007-10-13 at 16:17 +0200, J. Mayer wrote: > > > On Sat, 2007-10-13 at 16:07 +0300, Blue Swirl wrote: > > > > On 10/13/07, J. Mayer wrote: > > > > > On Sat, 2007-10-13 at 13:47 +0300, Blue Swirl wrote: > > > > > > On 10/13/07, J. Mayer wrote: > > > > > > > The problem: > > > > > > > some CPU architectures, namely PowerPC and maybe others, offers > > > > > > > facilities to access the memory or I/O in the reverse endianness, ie > > > > > > > little-endian instead of big-endian for PowerPC, or provide instruction > > > > > > > to make memory accesses in the "reverse-endian". This is implemented as > > > > > > > a global flag on some CPU. This case is already handled by the PowerPC > > > > > > > emulation but is is far from being optimal. Some other implementations > > > > > > > allow the OS to store an "reverse-endian" flag in the TLB or the segment > > > > > > > descriptors, thus providing per-page or per-segment endianness control. > > > > > > > This is mostly used to ease driver migration from a PC platform to > > > > > > > PowerPC without taking any care of the device endianness in the driver > > > > > > > code (yes, this is bad...). > > > > > > > > > > > > Nice, this may be useful for Sparc64. It has a global CPU flag for > > > > > > endianness, individual pages can be marked as reverse endian, and > > > > > > finally there are instructions that access memory in reverse endian. > > > > > > The end result is a XOR of all these reverses. Though I don't know if > > > > > > any of these features are used at all. > > > > > > > > > > I realized that I/O accesses for reverse-endian pages were not correct > > > > > in the softmmu_template.h header. This new version fixes this. It also > > > > > remove duplicated code in the case of unaligned accesses in a > > > > > reverse-endian page. > > > > > > > > I think 64 bit access case is not handled correctly, but to solve that > > > > it would be nice to extend the current IO access system to 64 bits. > > > > > > I think that if it was previously correct, it should still be, but... I > > > don't know how much having 64 bits I/O accesses is interresting, as I > > > don't know if there are real hw buses that have 64 bits data path... > > > > > > Here's another version taking care of your remark about ldl memory > > > accessors. > > > * I replaced all ldl occurences with ldul > > > * when TARGET_LONG_BITS == 64, I also added ldsl accessors. And I > > > started using it in the PowerPC memory access micro-ops. > > > Then the patch is really more invasive than the previous ones. > > > This still does not break PowerPC or i386 target, as it seems. > > > > Here's a new version. The only change is that, for consistency, I did > > add the big-endian and little-endian accessors that were documented in > > cpu-all.h as unimplemented. The implementation is quite trivial, having > > native and reverse-endian accessors available, and changes functionnally > > nothing to the previous version. > > The patch does not apply anymore. The Sparc part looks OK. > > The benefits from the patch can be gained by mapping Sparc64 lduw and > ldsw in op_mem.h directly to ldul and ldsl using SPARC_LD_OP and > replacing the ldl+bswap etc. for the LE cases with ldlr in > op_helper.c. If you prefer, I can do this after you have applied the > patch. Yes, there are conflicts between this patch and the mmu_idx one I just commited. I will regenerate an updated diff in the hours to come, after I finished commiting the PowerPC fixes and improvments I got waiting in stock. For the Sparc improvments, as I merged the PowerPC improvments in the patch, I think it can be a good idea to include it directly in the patch. I'm also wondering if it would not be a good idea to define lduq/ldsq even if they in fact do exactly what ldq does now, just to have a fully consistent API. -- J. Mayer Never organized