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[200.56.192.86]) by smtp.gmail.com with ESMTPSA id s110sm1021947otb.34.2019.06.07.11.08.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 07 Jun 2019 11:08:24 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20190606174609.20487-1-peter.maydell@linaro.org> <20190606174609.20487-14-peter.maydell@linaro.org> From: Richard Henderson Openpgp: preference=signencrypt Message-ID: <119282bd-4a60-e9a6-99c2-4fa2ddb1ecc0@linaro.org> Date: Fri, 7 Jun 2019 13:08:21 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <20190606174609.20487-14-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::341 Subject: Re: [Qemu-devel] [PATCH 13/42] target/arm: Convert "single-precision" register moves to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/6/19 12:45 PM, Peter Maydell wrote: > Convert the "single-precision" register moves to decodetree: > * VMSR > * VMRS > * VMOV between general purpose register and single precision > > Note that the VMSR/VMRS conversions make our handling of > the "should this UNDEF?" checks consistent between the two > instructions: > * VMSR to MVFR0, MVFR1, MVFR2 now UNDEF from EL0 > (previously was a nop) > * VMSR to FPSID now UNDEFs from EL0 or if VFPv3 or better > (previously was a nop) > * VMSR to FPINST and FPINST2 now UNDEF if VFPv3 or better > (previously would write to the register, which had no > guest-visible effect because we always UNDEF reads) > > We also tighten up the decode: we were previously underdecoding > some SBZ or SBO bits. > > The conversion of VMOV_single includes the expansion out of the > gen_mov_F0_vreg()/gen_vfp_mrs() and gen_mov_vreg_F0()/gen_vfp_msr() > sequences into the simpler direct load/store of the TCG temp via > neon_{load,store}_reg32(): we know in the new function that we're > always single-precision, we don't need to use the old-and-deprecated > cpu_F0* TCG globals, and we don't happen to have the declaration of > gen_vfp_msr() and gen_vfp_mrs() at the point in the file where the > new function is. > > Signed-off-by: Peter Maydell > --- > target/arm/translate-vfp.inc.c | 161 +++++++++++++++++++++++++++++++++ > target/arm/translate.c | 148 +----------------------------- > target/arm/vfp.decode | 4 + > 3 files changed, 168 insertions(+), 145 deletions(-) Reviewed-by: Richard Henderson r~