Re: [Qemu-devel] I got a kernel booted under qemu-system-ppc !

["J. Mayer" <l_indien@magic.fr>]

On Sun, 2007-10-21 at 12:24 +0200, J. Mayer wrote:
> On Sun, 2007-10-21 at 04:55 -0500, Rob Landley wrote:
> > On Saturday 20 October 2007 3:50:52 am J. Mayer wrote:
[...]
> > > And you can get the list of all CPUs emulated by Qemu with the '-cpu ?'
> > > switch.
> > 
> > I did that, but it -cpu ? gives output like:
> > 
> >   PowerPC 7448             PVR 80040201
> >   PowerPC 7448v1.0         PVR 80040100
> >   PowerPC 7448v1.1         PVR 80040101
> >   PowerPC 7448v2.0         PVR 80040200
> >   PowerPC 7448v2.1         PVR 80040201
> > 
> > I prefer the result of "-M ?" which makes it slightly clearer which field you 
> > need to feed qemu as an argument.  (For the record, -cpu seems to want filed 
> > $2 of the -cpu ? output.)  Also, that doesn't tell me what the differences 
> > between any of them are.
> 
> The idea of showing the name of the model and the PVR (processor version
> register) is that it can be useful to give Qemu a PVR instead of a name,
> even if this possibility is not properly implemented in the commited
> version. It's sometime more relevant to provide a PVR than a core name,
> imho...

Something I forgot to say is that this output is supposed to give a help
to the end-user. It seems to me that showing the CPU family (ie PowerPC)
can be useful when POWER and RS64 families will be emulated too, in
order to help the user choose which CPU to emulate.

> I will put a dump of the CPU features for all cores emulated by Qemu on
> line soon.

Here you'll find a reference for all PowerPC CPUs / cores /
microcontrollers available with the Qemu -cpu switch. Hope I did not
forget anything.
<http://perso.magic.fr/l_indien/qemu-ppc/PowerPC_ref/PowerPC_ref.html>
For each CPU, you get:
- its name, as provided with the Qemu -cpu switch
- its PVR (processor version register)
- the bits defined in the MSR (machine state register)
- its MMU model and the TLB model when relevant
- its exception handling model
- its input bus model
- the specific features provided by the MSR
- its complete instructions set (only one insn is dumped when 2
instructions share the same opcode)
- the complete list of SPRs (special purpose registers) with access
rights in supervisor and user mode

[...]

-- 
J. Mayer <l_indien@magic.fr>
Never organized