From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Ikdfq-0001cS-Sj for qemu-devel@nongnu.org; Wed, 24 Oct 2007 06:41:18 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Ikdfp-0001at-U2 for qemu-devel@nongnu.org; Wed, 24 Oct 2007 06:41:18 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Ikdfp-0001ai-LN for qemu-devel@nongnu.org; Wed, 24 Oct 2007 06:41:17 -0400 Received: from honiara.magic.fr ([195.154.193.36]) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Ikdfo-0002X3-QO for qemu-devel@nongnu.org; Wed, 24 Oct 2007 06:41:17 -0400 Received: from [192.168.0.2] (ppp-36.net-123.static.magiconline.fr [80.118.184.36]) by honiara.magic.fr (8.13.1/8.13.1) with ESMTP id l9OAfCbM017380 for ; Wed, 24 Oct 2007 12:41:12 +0200 From: "J. Mayer" Content-Type: text/plain Date: Wed, 24 Oct 2007 12:41:14 +0200 Message-Id: <1193222474.16781.236.camel@rapid> Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] Mips 64 emulation not compiling Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel The latest patches in clo makes gcc 3.4.6 fail to build the mips64 targets on my amd64 host (looks like an register allocation clash in the optimizer code). Furthermore, the clz micro-op for Mips seems very suspect to me, according to the changes made in the clo implementation. I did change the clz / clo implementation to use the same code as the one used for the PowerPC implementation. It seems to me that the result would be correct... And it compiles... Please take a look to the folowing patch: Index: target-mips/op.c =================================================================== RCS file: /sources/qemu/qemu/target-mips/op.c,v retrieving revision 1.80 diff -u -d -d -p -r1.80 op.c --- target-mips/op.c 24 Oct 2007 00:10:32 -0000 1.80 +++ target-mips/op.c 24 Oct 2007 10:38:26 -0000 @@ -535,37 +535,44 @@ void op_rotrv (void) RETURN(); } -void op_clo (void) +static always_inline int _do_cntlzw (uint32_t val) { - int n; - - if (T0 == ~((target_ulong)0)) { - T0 = 32; - } else { - for (n = 0; n < 32; n++) { - if (!(((int32_t)T0) & (1 << 31))) - break; - T0 <<= 1; - } - T0 = n; + int cnt = 0; + if (!(val & 0xFFFF0000UL)) { + cnt += 16; + val <<= 16; + } + if (!(val & 0xFF000000UL)) { + cnt += 8; + val <<= 8; } + if (!(val & 0xF0000000UL)) { + cnt += 4; + val <<= 4; + } + if (!(val & 0xC0000000UL)) { + cnt += 2; + val <<= 2; + } + if (!(val & 0x80000000UL)) { + cnt++; + val <<= 1; + } + if (!(val & 0x80000000UL)) { + cnt++; + } + return cnt; +} + +void op_clo (void) +{ + T0 = _do_cntlzw(~T0); RETURN(); } void op_clz (void) { - int n; - - if (T0 == 0) { - T0 = 32; - } else { - for (n = 0; n < 32; n++) { - if (T0 & (1 << 31)) - break; - T0 <<= 1; - } - T0 = n; - } + T0 = _do_cntlzw(T0); RETURN(); } -- J. Mayer Never organized