From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43)
	id 1J2coV-0008Ve-EZ
	for qemu-devel@nongnu.org; Wed, 12 Dec 2007 20:24:35 -0500
Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43)
	id 1J2coT-0008Ux-Ik
	for qemu-devel@nongnu.org; Wed, 12 Dec 2007 20:24:34 -0500
Received: from [199.232.76.173] (helo=monty-python.gnu.org)
	by lists.gnu.org with esmtp (Exim 4.43) id 1J2coT-0008Ur-8x
	for qemu-devel@nongnu.org; Wed, 12 Dec 2007 20:24:33 -0500
Received: from owa.c2.net ([207.235.78.2] helo=email.c2.net)
	by monty-python.gnu.org with esmtp (Exim 4.60)
	(envelope-from <thayne@c2.net>) id 1J2coS-0000Il-Vt
	for qemu-devel@nongnu.org; Wed, 12 Dec 2007 20:24:33 -0500
Subject: Re: [Qemu-devel] [PATCH] arm eabi TLS
From: Thayne Harbaugh <thayne@c2.net>
In-Reply-To: <200712130121.04204.paul@codesourcery.com>
References: <1197420297.2947.94.camel@phantasm.home.enterpriseandprosperity.com>
	<476068AA.80001@bellard.org> <200712130121.04204.paul@codesourcery.com>
Content-Type: text/plain
Date: Wed, 12 Dec 2007 18:15:40 -0700
Message-Id: <1197508540.3640.2.camel@phantasm.home.enterpriseandprosperity.com>
Mime-Version: 1.0
Content-Transfer-Encoding: 7bit
Reply-To: thayne@c2.net, qemu-devel@nongnu.org
List-Id: qemu-devel.nongnu.org
List-Unsubscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.gnu.org/pipermail/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Paul Brook <paul@codesourcery.com>
Cc: qemu-devel@nongnu.org


On Thu, 2007-12-13 at 01:21 +0000, Paul Brook wrote:
> > - It would be good to limit the changes in the CPU emulation code to
> > handle the TLS. For example, on MIPS, the TLS register must not be
> > stored in the CPU state. Same for ARM.
> 
> I disagree. The TLS register is part of the CPU state. On many machines 
> (including ARMv6 CPUs) it's an actual CPU register. I'm fairly sure the same 
> is true for recent MIPS revisions.

I agree with Paul.  Some archs actually use a CPU register and require
the kernel to help manage TLS.  Other archs can manage TLS completely in
user space.  It's been a while since I've investigated all the details
for each arch but I'll go review it.