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[174.21.76.60]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7c3f0b63dbcsm15469070b3a.50.2025.11.24.11.46.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Nov 2025 11:46:15 -0800 (PST) Message-ID: <119ec250-2532-452d-a8f8-0fdbb2f1a8b8@linaro.org> Date: Mon, 24 Nov 2025 11:46:13 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/3] target/arm: Enable ID_AA64MMFR4_EL1 register. To: Jim MacArthur , qemu-devel@nongnu.org References: <20251120125833.123813-1-jim.macarthur@linaro.org> <20251120125833.123813-2-jim.macarthur@linaro.org> From: Richard Henderson Content-Language: en-US In-Reply-To: <20251120125833.123813-2-jim.macarthur@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/20/25 04:54, Jim MacArthur wrote: > Signed-off-by: Jim MacArthur > --- > target/arm/cpu-sysregs.h.inc | 1 + > target/arm/helper.c | 4 ++-- > 2 files changed, 3 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson r~> > diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc > index 2bb2861c62..2ba49d8478 100644 > --- a/target/arm/cpu-sysregs.h.inc > +++ b/target/arm/cpu-sysregs.h.inc > @@ -14,6 +14,7 @@ DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0) > DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1) > DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2) > DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3) > +DEF(ID_AA64MMFR4_EL1, 3, 0, 0, 7, 4) > DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0) > DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1) > DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2) > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 27ebc6f29b..c20334fa65 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6566,11 +6566,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) > .access = PL1_R, .type = ARM_CP_CONST, > .accessfn = access_aa64_tid3, > .resetvalue = GET_IDREG(isar, ID_AA64MMFR3) }, > - { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, > + { .name = "ID_AA64MMFR4_EL1", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, > .access = PL1_R, .type = ARM_CP_CONST, > .accessfn = access_aa64_tid3, > - .resetvalue = 0 }, > + .resetvalue = GET_IDREG(isar, ID_AA64MMFR4) }, > { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5, > .access = PL1_R, .type = ARM_CP_CONST,