[PATCH v3 0/4] Cavium Octeon MIPS extensions

[PATCH v3 0/4] Cavium Octeon MIPS extensions

[Pavel Dovgalyuk]

The following series includes emulation of the platform-specific MIPS extension
for Cavium Octeon CPUS:
- basic Octeon vCPU model
- custom instruction decoder for Octeon
- implementation of arithmetic and logic instructions

v3 changes:
 - separated vCPU model definition and decodetree for Octeon
   (suggested by Philippe Mathieu-Daudé)
 - fixed length field for EXTS/CINS (bug found by Richard Henderson)

v2 changes:
 - simplified instruction decoding and translation (suggested by Richard Henderson)

---

Pavel Dovgalyuk (4):
      target/mips: introduce decodetree structure for Cavium Octeon extension
      target/mips: implement Octeon-specific BBIT instructions
      target/mips: implement Octeon-specific arithmetic instructions
      target/mips: introduce Cavium Octeon CPU model


 target/mips/cpu-defs.c.inc         |  28 +++++
 target/mips/tcg/octeon.decode      |  35 ++++++
 target/mips/tcg/octeon_translate.c | 185 +++++++++++++++++++++++++++++
 3 files changed, 248 insertions(+)

--
Pavel Dovgalyuk

[PATCH v3 1/4] target/mips: introduce decodetree structure for Cavium Octeon extension

[Pavel Dovgalyuk]

This patch adds decodetree for Cavium Octeon extension and
an instruction set extension flag for using it in CPU models.

Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
---
 target/mips/mips-defs.h            |    1 +
 target/mips/tcg/meson.build        |    2 ++
 target/mips/tcg/octeon.decode      |    6 ++++++
 target/mips/tcg/octeon_translate.c |   16 ++++++++++++++++
 target/mips/tcg/translate.c        |    5 +++++
 target/mips/tcg/translate.h        |    1 +
 6 files changed, 31 insertions(+)
 create mode 100644 target/mips/tcg/octeon.decode
 create mode 100644 target/mips/tcg/octeon_translate.c

diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 0a12d982a7..a6cebe0265 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -42,6 +42,7 @@
 #define INSN_LOONGSON2E   0x0000040000000000ULL
 #define INSN_LOONGSON2F   0x0000080000000000ULL
 #define INSN_LOONGSON3A   0x0000100000000000ULL
+#define INSN_OCTEON       0x0000200000000000ULL
 /*
  *   bits 52-63: vendor-specific ASEs
  */
diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build
index 98003779ae..7ee969ec8f 100644
--- a/target/mips/tcg/meson.build
+++ b/target/mips/tcg/meson.build
@@ -3,6 +3,7 @@ gen = [
   decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'),
   decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'),
   decodetree.process('vr54xx.decode', extra_args: '--decode=decode_ext_vr54xx'),
+  decodetree.process('octeon.decode', extra_args: '--decode=decode_ext_octeon'),
 ]
 
 mips_ss.add(gen)
@@ -24,6 +25,7 @@ mips_ss.add(files(
 ))
 mips_ss.add(when: 'TARGET_MIPS64', if_true: files(
   'tx79_translate.c',
+  'octeon_translate.c',
 ), if_false: files(
   'mxu_translate.c',
 ))
diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode
new file mode 100644
index 0000000000..b21c735a6c
--- /dev/null
+++ b/target/mips/tcg/octeon.decode
@@ -0,0 +1,6 @@
+# Octeon Architecture Module instruction set
+#
+# Copyright (C) 2022 Pavel Dovgalyuk
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c
new file mode 100644
index 0000000000..8b5eb1a823
--- /dev/null
+++ b/target/mips/tcg/octeon_translate.c
@@ -0,0 +1,16 @@
+/*
+ * Octeon-specific instructions translation routines
+ *
+ *  Copyright (c) 2022 Pavel Dovgalyuk
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "tcg/tcg-op.h"
+#include "tcg/tcg-op-gvec.h"
+#include "exec/helper-gen.h"
+#include "translate.h"
+
+/* Include the auto-generated decoder.  */
+#include "decode-octeon.c.inc"
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 5f460fb687..f4345ce0c7 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -15963,6 +15963,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
     if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx, ctx->opcode)) {
         return;
     }
+#if defined(TARGET_MIPS64)
+    if (cpu_supports_isa(env, INSN_OCTEON) && decode_ext_octeon(ctx, ctx->opcode)) {
+        return;
+    }
+#endif
 
     /* ISA extensions */
     if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) {
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index 9997fe2f3c..55053226ae 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -215,6 +215,7 @@ bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
 bool decode_ext_txx9(DisasContext *ctx, uint32_t insn);
 #if defined(TARGET_MIPS64)
 bool decode_ext_tx79(DisasContext *ctx, uint32_t insn);
+bool decode_ext_octeon(DisasContext *ctx, uint32_t insn);
 #endif
 bool decode_ext_vr54xx(DisasContext *ctx, uint32_t insn);
 

Re: [PATCH v3 1/4] target/mips: introduce decodetree structure for Cavium Octeon extension

[Richard Henderson]

On 6/20/22 05:05, Pavel Dovgalyuk wrote:
> This patch adds decodetree for Cavium Octeon extension and
> an instruction set extension flag for using it in CPU models.
> 
> Signed-off-by: Pavel Dovgalyuk<Pavel.Dovgalyuk@ispras.ru>
> ---
>   target/mips/mips-defs.h            |    1 +
>   target/mips/tcg/meson.build        |    2 ++
>   target/mips/tcg/octeon.decode      |    6 ++++++
>   target/mips/tcg/octeon_translate.c |   16 ++++++++++++++++
>   target/mips/tcg/translate.c        |    5 +++++
>   target/mips/tcg/translate.h        |    1 +
>   6 files changed, 31 insertions(+)
>   create mode 100644 target/mips/tcg/octeon.decode
>   create mode 100644 target/mips/tcg/octeon_translate.c

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[PATCH v3 2/4] target/mips: implement Octeon-specific BBIT instructions

[Pavel Dovgalyuk]

This patch introduces Octeon-specific decoder and implements
check-bit-and-jump instructions.

Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

--

v3 changes:
     - Split new decodetree and BBIT decoding into two patches
       (suggested by Philippe Mathieu-Daudé)
v2 changes:
     - Changed insn field description and simplified the jumps
       (suggested by Richard Henderson)
---
 target/mips/tcg/octeon.decode      |    9 +++++++++
 target/mips/tcg/octeon_translate.c |   30 ++++++++++++++++++++++++++++++
 2 files changed, 39 insertions(+)

diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode
index b21c735a6c..8062715578 100644
--- a/target/mips/tcg/octeon.decode
+++ b/target/mips/tcg/octeon.decode
@@ -4,3 +4,12 @@
 #
 # SPDX-License-Identifier: LGPL-2.1-or-later
 #
+
+# Branch on bit set or clear
+# BBIT0      110010 ..... ..... ................
+# BBIT032    110110 ..... ..... ................
+# BBIT1      111010 ..... ..... ................
+# BBIT132    111110 ..... ..... ................
+
+%bbit_p      28:1 16:5
+BBIT         11 set:1 . 10 rs:5 ..... offset:16 p=%bbit_p
diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c
index 8b5eb1a823..1558f74a8e 100644
--- a/target/mips/tcg/octeon_translate.c
+++ b/target/mips/tcg/octeon_translate.c
@@ -14,3 +14,33 @@
 
 /* Include the auto-generated decoder.  */
 #include "decode-octeon.c.inc"
+
+static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)
+{
+    TCGv p;
+
+    if (ctx->hflags & MIPS_HFLAG_BMASK) {
+        LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
+                  TARGET_FMT_lx "\n", ctx->base.pc_next);
+        generate_exception_end(ctx, EXCP_RI);
+        return true;
+    }
+
+    /* Load needed operands */
+    TCGv t0 = tcg_temp_new();
+    gen_load_gpr(t0, a->rs);
+
+    p = tcg_constant_tl(1ULL << a->p);
+    if (a->set) {
+        tcg_gen_and_tl(bcond, p, t0);
+    } else {
+        tcg_gen_andc_tl(bcond, p, t0);
+    }
+
+    ctx->hflags |= MIPS_HFLAG_BC;
+    ctx->btarget = ctx->base.pc_next + 4 + a->offset * 4;
+    ctx->hflags |= MIPS_HFLAG_BDS32;
+
+    tcg_temp_free(t0);
+    return true;
+}

[PATCH v3 3/4] target/mips: implement Octeon-specific arithmetic instructions

[Pavel Dovgalyuk]

This patch implements several Octeon-specific instructions:
- BADDU
- DMUL
- EXTS/EXTS32
- CINS/CINS32
- POP/DPOP
- SEQ/SEQI
- SNE/SNEI

Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>

--

v3 changes:
   - Fixed length field for EXTS/CINS
     (bug found by Richard Henderson)
v2 changes:
   - Using existing tcg instructions for exts, cins, pop
     (suggested by Richard Henderson)
---
 target/mips/tcg/octeon.decode      |   26 ++++++
 target/mips/tcg/octeon_translate.c |  155 ++++++++++++++++++++++++++++++++++++
 2 files changed, 181 insertions(+)

diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode
index 8062715578..8929ad088e 100644
--- a/target/mips/tcg/octeon.decode
+++ b/target/mips/tcg/octeon.decode
@@ -13,3 +13,29 @@
 
 %bbit_p      28:1 16:5
 BBIT         11 set:1 . 10 rs:5 ..... offset:16 p=%bbit_p
+
+# Arithmetic
+# BADDU rd, rs, rt
+# DMUL rd, rs, rt
+# EXTS rt, rs, p, lenm1
+# EXTS32 rt, rs, p, lenm1
+# CINS rt, rs, p, lenm1
+# CINS32 rt, rs, p, lenm1
+# DPOP rd, rs
+# POP rd, rs
+# SEQ rd, rs, rt
+# SEQI rt, rs, immediate
+# SNE rd, rs, rt
+# SNEI rt, rs, immediate
+
+@r3          ...... rs:5 rt:5 rd:5 ..... ......
+%bitfield_p  0:1 6:5
+@bitfield    ...... rs:5 rt:5 lenm1:5 ..... ..... . p=%bitfield_p
+
+BADDU        011100 ..... ..... ..... 00000 101000 @r3
+DMUL         011100 ..... ..... ..... 00000 000011 @r3
+EXTS         011100 ..... ..... ..... ..... 11101 . @bitfield
+CINS         011100 ..... ..... ..... ..... 11001 . @bitfield
+POP          011100 rs:5 00000 rd:5 00000 10110 dw:1
+SEQNE        011100 rs:5 rt:5 rd:5 00000 10101 ne:1
+SEQNEI       011100 rs:5 rt:5 imm:s10 10111 ne:1
diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c
index 1558f74a8e..6a207d2e7e 100644
--- a/target/mips/tcg/octeon_translate.c
+++ b/target/mips/tcg/octeon_translate.c
@@ -44,3 +44,158 @@ static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)
     tcg_temp_free(t0);
     return true;
 }
+
+static bool trans_BADDU(DisasContext *ctx, arg_BADDU *a)
+{
+    TCGv t0, t1;
+
+    if (a->rt == 0) {
+        /* nop */
+        return true;
+    }
+
+    t0 = tcg_temp_new();
+    t1 = tcg_temp_new();
+    gen_load_gpr(t0, a->rs);
+    gen_load_gpr(t1, a->rt);
+
+    tcg_gen_add_tl(t0, t0, t1);
+    tcg_gen_andi_i64(cpu_gpr[a->rd], t0, 0xff);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(t1);
+
+    return true;
+}
+
+static bool trans_DMUL(DisasContext *ctx, arg_DMUL *a)
+{
+    TCGv t0, t1;
+
+    if (a->rt == 0) {
+        /* nop */
+        return true;
+    }
+
+    t0 = tcg_temp_new();
+    t1 = tcg_temp_new();
+    gen_load_gpr(t0, a->rs);
+    gen_load_gpr(t1, a->rt);
+
+    tcg_gen_mul_i64(cpu_gpr[a->rd], t0, t1);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(t1);
+
+    return true;
+}
+
+static bool trans_EXTS(DisasContext *ctx, arg_EXTS *a)
+{
+    TCGv t0;
+
+    if (a->rt == 0) {
+        /* nop */
+        return true;
+    }
+
+    t0 = tcg_temp_new();
+    gen_load_gpr(t0, a->rs);
+    tcg_gen_sextract_tl(t0, t0, a->p, a->lenm1 + 1);
+    gen_store_gpr(t0, a->rt);
+    tcg_temp_free(t0);
+
+    return true;
+}
+
+static bool trans_CINS(DisasContext *ctx, arg_CINS *a)
+{
+    TCGv t0;
+
+    if (a->rt == 0) {
+        /* nop */
+        return true;
+    }
+
+    t0 = tcg_temp_new();
+    gen_load_gpr(t0, a->rs);
+    tcg_gen_deposit_z_tl(t0, t0, a->p, a->lenm1 + 1);
+    gen_store_gpr(t0, a->rt);
+    tcg_temp_free(t0);
+
+    return true;
+}
+
+static bool trans_POP(DisasContext *ctx, arg_POP *a)
+{
+    TCGv t0;
+
+    if (a->rd == 0) {
+        /* nop */
+        return true;
+    }
+
+    t0 = tcg_temp_new();
+    gen_load_gpr(t0, a->rs);
+    if (!a->dw) {
+        tcg_gen_andi_i64(t0, t0, 0xffffffff);
+    }
+    tcg_gen_ctpop_tl(t0, t0);
+    gen_store_gpr(t0, a->rd);
+    tcg_temp_free(t0);
+
+    return true;
+}
+
+static bool trans_SEQNE(DisasContext *ctx, arg_SEQNE *a)
+{
+    TCGv t0, t1;
+
+    if (a->rd == 0) {
+        /* nop */
+        return true;
+    }
+
+    t0 = tcg_temp_new();
+    t1 = tcg_temp_new();
+
+    gen_load_gpr(t0, a->rs);
+    gen_load_gpr(t1, a->rt);
+
+    if (a->ne) {
+        tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr[a->rd], t1, t0);
+    } else {
+        tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr[a->rd], t1, t0);
+    }
+
+    tcg_temp_free(t0);
+    tcg_temp_free(t1);
+
+    return true;
+}
+
+static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNEI *a)
+{
+    TCGv t0;
+
+    if (a->rt == 0) {
+        /* nop */
+        return true;
+    }
+
+    t0 = tcg_temp_new();
+
+    gen_load_gpr(t0, a->rs);
+
+    /* Sign-extend to 64 bit value */
+    target_ulong imm = a->imm;
+    if (a->ne) {
+        tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr[a->rt], t0, imm);
+    } else {
+        tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm);
+    }
+
+    tcg_temp_free(t0);
+
+    return true;
+}

Re: [PATCH v3 3/4] target/mips: implement Octeon-specific arithmetic instructions

[Richard Henderson]

On 6/20/22 05:05, Pavel Dovgalyuk wrote:
> This patch implements several Octeon-specific instructions:
> - BADDU
> - DMUL
> - EXTS/EXTS32
> - CINS/CINS32
> - POP/DPOP
> - SEQ/SEQI
> - SNE/SNEI
> 
> Signed-off-by: Pavel Dovgalyuk<Pavel.Dovgalyuk@ispras.ru>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[PATCH v3 4/4] target/mips: introduce Cavium Octeon CPU model

[Pavel Dovgalyuk]

This patch adds Cavium Octeon 68XX vCPU which provides
Octeon-specific instructions.

Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>

--
v3 changes:
 - split the patch to instruction set introduction and new vCPU
   (suggested by Philippe Mathieu-Daudé)
v2 changes:
 - vCPU name changed to Octeon68XX (suggested by Richard Henderson)
---
 target/mips/cpu-defs.c.inc |   28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index 582f940070..7f53c94ec8 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -921,6 +921,34 @@ const mips_def_t mips_defs[] =
         .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
         .mmu_type = MMU_TYPE_R4000,
     },
+    {
+        /*
+         * Octeon 68xx with MIPS64 Cavium Octeon features.
+         */
+        .name = "Octeon68XX",
+        .CP0_PRid = 0x000D9100,
+        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
+                       (MMU_TYPE_R4000 << CP0C0_MT),
+        .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
+                       (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
+                       (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
+                       (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+        .CP0_Config2 = MIPS_CONFIG2,
+        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA) | (1 << CP0C3_DSPP) ,
+        .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) |
+                       (0x3c << CP0C4_KScrExist) | (1U << CP0C4_MMUExtDef) |
+                       (3U << CP0C4_MMUSizeExt),
+        .CP0_LLAddr_rw_bitmask = 0,
+        .CP0_LLAddr_shift = 4,
+        .CP0_PageGrain = (1 << CP0PG_ELPA),
+        .SYNCI_Step = 32,
+        .CCRes = 2,
+        .CP0_Status_rw_bitmask = 0x12F8FFFF,
+        .SEGBITS = 42,
+        .PABITS = 49,
+        .insn_flags = CPU_MIPS64R2 | INSN_OCTEON | ASE_DSP,
+        .mmu_type = MMU_TYPE_R4000,
+    },
 
 #endif
 };

Re: [PATCH v3 4/4] target/mips: introduce Cavium Octeon CPU model

[Pavel Dovgalyuk]

ping

This is the only non-reviewed patch in the series.

On 20.06.2022 15:05, Pavel Dovgalyuk wrote:
> This patch adds Cavium Octeon 68XX vCPU which provides
> Octeon-specific instructions.
> 
> Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
> 
> --
> v3 changes:
>   - split the patch to instruction set introduction and new vCPU
>     (suggested by Philippe Mathieu-Daudé)
> v2 changes:
>   - vCPU name changed to Octeon68XX (suggested by Richard Henderson)
> ---
>   target/mips/cpu-defs.c.inc |   28 ++++++++++++++++++++++++++++
>   1 file changed, 28 insertions(+)
> 
> diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
> index 582f940070..7f53c94ec8 100644
> --- a/target/mips/cpu-defs.c.inc
> +++ b/target/mips/cpu-defs.c.inc
> @@ -921,6 +921,34 @@ const mips_def_t mips_defs[] =
>           .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
>           .mmu_type = MMU_TYPE_R4000,
>       },
> +    {
> +        /*
> +         * Octeon 68xx with MIPS64 Cavium Octeon features.
> +         */
> +        .name = "Octeon68XX",
> +        .CP0_PRid = 0x000D9100,
> +        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
> +                       (MMU_TYPE_R4000 << CP0C0_MT),
> +        .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
> +                       (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
> +                       (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
> +                       (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
> +        .CP0_Config2 = MIPS_CONFIG2,
> +        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA) | (1 << CP0C3_DSPP) ,
> +        .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) |
> +                       (0x3c << CP0C4_KScrExist) | (1U << CP0C4_MMUExtDef) |
> +                       (3U << CP0C4_MMUSizeExt),
> +        .CP0_LLAddr_rw_bitmask = 0,
> +        .CP0_LLAddr_shift = 4,
> +        .CP0_PageGrain = (1 << CP0PG_ELPA),
> +        .SYNCI_Step = 32,
> +        .CCRes = 2,
> +        .CP0_Status_rw_bitmask = 0x12F8FFFF,
> +        .SEGBITS = 42,
> +        .PABITS = 49,
> +        .insn_flags = CPU_MIPS64R2 | INSN_OCTEON | ASE_DSP,
> +        .mmu_type = MMU_TYPE_R4000,
> +    },
>   
>   #endif
>   };
> 

Re: [PATCH v3 4/4] target/mips: introduce Cavium Octeon CPU model

[Philippe Mathieu-Daudé via]

On 4/7/22 12:59, Pavel Dovgalyuk wrote:
> ping
> 
> This is the only non-reviewed patch in the series.

I've been looking for doc/datasheets but no luck (except the Linux 
kernel comments).

What kind of testing are you doing?

> On 20.06.2022 15:05, Pavel Dovgalyuk wrote:
>> This patch adds Cavium Octeon 68XX vCPU which provides
>> Octeon-specific instructions.
>>
>> Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
>>
>> -- 
>> v3 changes:
>>   - split the patch to instruction set introduction and new vCPU
>>     (suggested by Philippe Mathieu-Daudé)
>> v2 changes:
>>   - vCPU name changed to Octeon68XX (suggested by Richard Henderson)
>> ---
>>   target/mips/cpu-defs.c.inc |   28 ++++++++++++++++++++++++++++
>>   1 file changed, 28 insertions(+)

Re: [PATCH v3 4/4] target/mips: introduce Cavium Octeon CPU model

[Pavel Dovgalyuk]

On 06.07.2022 23:53, Philippe Mathieu-Daudé wrote:
> On 4/7/22 12:59, Pavel Dovgalyuk wrote:
>> ping
>>
>> This is the only non-reviewed patch in the series.
> 
> I've been looking for doc/datasheets but no luck (except the Linux 
> kernel comments).
> 
> What kind of testing are you doing?

We compared the instruction emulation with the behavior on dev board.

> 
>> On 20.06.2022 15:05, Pavel Dovgalyuk wrote:
>>> This patch adds Cavium Octeon 68XX vCPU which provides
>>> Octeon-specific instructions.
>>>
>>> Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
>>>
>>> -- 
>>> v3 changes:
>>>   - split the patch to instruction set introduction and new vCPU
>>>     (suggested by Philippe Mathieu-Daudé)
>>> v2 changes:
>>>   - vCPU name changed to Octeon68XX (suggested by Richard Henderson)
>>> ---
>>>   target/mips/cpu-defs.c.inc |   28 ++++++++++++++++++++++++++++
>>>   1 file changed, 28 insertions(+)

Re: [PATCH v3 4/4] target/mips: introduce Cavium Octeon CPU model

[Pavel Dovgalyuk]

On 06.07.2022 23:53, Philippe Mathieu-Daudé wrote:
> On 4/7/22 12:59, Pavel Dovgalyuk wrote:
>> ping
>>
>> This is the only non-reviewed patch in the series.
> 
> I've been looking for doc/datasheets but no luck (except the Linux 
> kernel comments).
> 
> What kind of testing are you doing?

BTW, we found SDK here: https://github.com/amitmisra16/OCTEON-SDK


> 
>> On 20.06.2022 15:05, Pavel Dovgalyuk wrote:
>>> This patch adds Cavium Octeon 68XX vCPU which provides
>>> Octeon-specific instructions.
>>>
>>> Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
>>>
>>> -- 
>>> v3 changes:
>>>   - split the patch to instruction set introduction and new vCPU
>>>     (suggested by Philippe Mathieu-Daudé)
>>> v2 changes:
>>>   - vCPU name changed to Octeon68XX (suggested by Richard Henderson)
>>> ---
>>>   target/mips/cpu-defs.c.inc |   28 ++++++++++++++++++++++++++++
>>>   1 file changed, 28 insertions(+)