From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Jyw3m-0007ch-Bp for qemu-devel@nongnu.org; Wed, 21 May 2008 17:41:22 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Jyw3l-0007c7-E0 for qemu-devel@nongnu.org; Wed, 21 May 2008 17:41:21 -0400 Received: from [199.232.76.173] (port=51169 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Jyw3l-0007c3-8a for qemu-devel@nongnu.org; Wed, 21 May 2008 17:41:21 -0400 Received: from mx1.redhat.com ([66.187.233.31]:39253) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Jyw3k-0005p7-PO for qemu-devel@nongnu.org; Wed, 21 May 2008 17:41:21 -0400 From: Glauber Costa Date: Wed, 21 May 2008 18:40:52 -0300 Message-Id: <1211406053-18211-2-git-send-email-gcosta@redhat.com> In-Reply-To: <1211406053-18211-1-git-send-email-gcosta@redhat.com> References: <1211406053-18211-1-git-send-email-gcosta@redhat.com> Subject: [Qemu-devel] [PATCH 2/3] Push common interrupt variables to cpu-defs.h Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: kvm-devel@lists.sourceforge.net Some interrupt-related attributes, which includes the jmp_buf, are present in all, or almost all, architectures. So move them to common code in cpu-defs.h instead of replicating them everywhere Signed-off-by: Glauber Costa --- cpu-defs.h | 5 +++++ target-alpha/cpu.h | 3 --- target-arm/cpu.h | 2 -- target-cris/cpu.h | 2 -- target-i386/cpu.h | 3 --- target-m68k/cpu.h | 2 -- target-mips/cpu.h | 3 --- target-ppc/cpu.h | 3 --- target-sh4/cpu.h | 2 -- target-sparc/cpu.h | 2 -- 10 files changed, 5 insertions(+), 22 deletions(-) diff --git a/cpu-defs.h b/cpu-defs.h index c4389ed..bb00c80 100644 --- a/cpu-defs.h +++ b/cpu-defs.h @@ -159,6 +159,11 @@ typedef struct CPUTLBEntry { int nb_watchpoints; \ int watchpoint_hit; \ \ + /* Core interrupt code */ \ + jmp_buf jmp_env; \ + int exception_index; \ + int error_code; \ + \ void *next_cpu; /* next CPU sharing TB cache */ \ int cpu_index; /* CPU index (informative) */ \ /* user data */ \ diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index f8bbc70..b3c10d7 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -282,13 +282,10 @@ struct CPUAlphaState { /* Those resources are used only in Qemu core */ CPU_COMMON - jmp_buf jmp_env; int user_mode_only; /* user mode only simulation */ uint32_t hflags; int halted; - int exception_index; - int error_code; int interrupt_request; uint32_t features; diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 2ff25a5..60a7a64 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -156,8 +156,6 @@ typedef struct CPUARMState { void *irq_opaque; /* exception/interrupt handling */ - jmp_buf jmp_env; - int exception_index; int interrupt_request; int user_mode_only; int halted; diff --git a/target-cris/cpu.h b/target-cris/cpu.h index a26dd80..d45abea 100644 --- a/target-cris/cpu.h +++ b/target-cris/cpu.h @@ -124,7 +124,6 @@ typedef struct CPUCRISState { int cc_x_live; int cc_x; - int exception_index; int interrupt_request; int interrupt_vector; int fault_vector; @@ -164,7 +163,6 @@ typedef struct CPUCRISState { int user_mode_only; int halted; - jmp_buf jmp_env; CPU_COMMON } CPUCRISState; diff --git a/target-i386/cpu.h b/target-i386/cpu.h index eb784b4..c8a4559 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -553,9 +553,6 @@ typedef struct CPUX86State { uint64_t pat; /* exception/interrupt handling */ - jmp_buf jmp_env; - int exception_index; - int error_code; int exception_is_int; target_ulong exception_next_eip; target_ulong dr[8]; /* debug registers */ diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h index 732929b..ba36387 100644 --- a/target-m68k/cpu.h +++ b/target-m68k/cpu.h @@ -104,8 +104,6 @@ typedef struct CPUM68KState { uint32_t t1; /* exception/interrupt handling */ - jmp_buf jmp_env; - int exception_index; int interrupt_request; int user_mode_only; int halted; diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 49b7e63..08aad3e 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -411,9 +411,6 @@ struct CPUMIPSState { int32_t CP0_DESAVE; /* Qemu */ int interrupt_request; - jmp_buf jmp_env; - int exception_index; - int error_code; int user_mode_only; /* user mode only simulation */ uint32_t hflags; /* CPU State */ /* TMASK defines different execution modes */ diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 7f7916f..e9f9287 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -648,8 +648,6 @@ struct CPUPPCState { int bfd_mach; uint32_t flags; - int exception_index; - int error_code; int interrupt_request; uint32_t pending_interrupts; #if !defined(CONFIG_USER_ONLY) @@ -674,7 +672,6 @@ struct CPUPPCState { opc_handler_t *opcodes[0x40]; /* Those resources are used only in Qemu core */ - jmp_buf jmp_env; int user_mode_only; /* user mode only simulation */ target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */ target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */ diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index 72ac82f..534ada3 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -114,11 +114,9 @@ typedef struct CPUSH4State { uint32_t expevt; /* exception event register */ uint32_t intevt; /* interrupt event register */ - jmp_buf jmp_env; int user_mode_only; int interrupt_request; int halted; - int exception_index; CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */ tlb_t itlb[ITLB_SIZE]; /* instruction translation table */ void *intc_handle; diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index af0ebd1..b663fe2 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -214,9 +214,7 @@ typedef struct CPUSPARCState { uint32_t pil_in; /* incoming interrupt level bitmap */ int psref; /* enable fpu */ target_ulong version; - jmp_buf jmp_env; int user_mode_only; - int exception_index; int interrupt_index; int interrupt_request; int halted; -- 1.5.4.5