* [Qemu-devel] [PATCH 0/2] use halted attribute for x86
@ 2008-05-21 21:40 Glauber Costa
2008-05-21 21:40 ` [Qemu-devel] [PATCH 2/3] Push common interrupt variables to cpu-defs.h Glauber Costa
0 siblings, 1 reply; 4+ messages in thread
From: Glauber Costa @ 2008-05-21 21:40 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm-devel
Hey,
In the next two e-mails, I do some work to make x86 use the "halted" attribute
instead of (just) HF_HALTED_MASK. The mask definition is not removed, but it can be,
if you think this patch is acceptable.
The main goal is to make it closer to other architectures. It can be seen as the
preamble of an yet-to-be-released patch, in which I'll remove the ifdefs around
do_interrupt for cpu-exec(). That patches still have some caveats, so I decided to
release this first part first.
Hope you like it.
^ permalink raw reply [flat|nested] 4+ messages in thread
* [Qemu-devel] [PATCH 2/3] Push common interrupt variables to cpu-defs.h
2008-05-21 21:40 [Qemu-devel] [PATCH 0/2] use halted attribute for x86 Glauber Costa
@ 2008-05-21 21:40 ` Glauber Costa
2008-05-21 21:40 ` [Qemu-devel] [PATCH 3/3] use halted attribute for i386 too Glauber Costa
0 siblings, 1 reply; 4+ messages in thread
From: Glauber Costa @ 2008-05-21 21:40 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm-devel
Some interrupt-related attributes, which includes the jmp_buf,
are present in all, or almost all, architectures. So move them
to common code in cpu-defs.h instead of replicating them everywhere
Signed-off-by: Glauber Costa <gcosta@redhat.com>
---
cpu-defs.h | 5 +++++
target-alpha/cpu.h | 3 ---
target-arm/cpu.h | 2 --
target-cris/cpu.h | 2 --
target-i386/cpu.h | 3 ---
target-m68k/cpu.h | 2 --
target-mips/cpu.h | 3 ---
target-ppc/cpu.h | 3 ---
target-sh4/cpu.h | 2 --
target-sparc/cpu.h | 2 --
10 files changed, 5 insertions(+), 22 deletions(-)
diff --git a/cpu-defs.h b/cpu-defs.h
index c4389ed..bb00c80 100644
--- a/cpu-defs.h
+++ b/cpu-defs.h
@@ -159,6 +159,11 @@ typedef struct CPUTLBEntry {
int nb_watchpoints; \
int watchpoint_hit; \
\
+ /* Core interrupt code */ \
+ jmp_buf jmp_env; \
+ int exception_index; \
+ int error_code; \
+ \
void *next_cpu; /* next CPU sharing TB cache */ \
int cpu_index; /* CPU index (informative) */ \
/* user data */ \
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index f8bbc70..b3c10d7 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -282,13 +282,10 @@ struct CPUAlphaState {
/* Those resources are used only in Qemu core */
CPU_COMMON
- jmp_buf jmp_env;
int user_mode_only; /* user mode only simulation */
uint32_t hflags;
int halted;
- int exception_index;
- int error_code;
int interrupt_request;
uint32_t features;
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 2ff25a5..60a7a64 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -156,8 +156,6 @@ typedef struct CPUARMState {
void *irq_opaque;
/* exception/interrupt handling */
- jmp_buf jmp_env;
- int exception_index;
int interrupt_request;
int user_mode_only;
int halted;
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index a26dd80..d45abea 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -124,7 +124,6 @@ typedef struct CPUCRISState {
int cc_x_live;
int cc_x;
- int exception_index;
int interrupt_request;
int interrupt_vector;
int fault_vector;
@@ -164,7 +163,6 @@ typedef struct CPUCRISState {
int user_mode_only;
int halted;
- jmp_buf jmp_env;
CPU_COMMON
} CPUCRISState;
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index eb784b4..c8a4559 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -553,9 +553,6 @@ typedef struct CPUX86State {
uint64_t pat;
/* exception/interrupt handling */
- jmp_buf jmp_env;
- int exception_index;
- int error_code;
int exception_is_int;
target_ulong exception_next_eip;
target_ulong dr[8]; /* debug registers */
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index 732929b..ba36387 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -104,8 +104,6 @@ typedef struct CPUM68KState {
uint32_t t1;
/* exception/interrupt handling */
- jmp_buf jmp_env;
- int exception_index;
int interrupt_request;
int user_mode_only;
int halted;
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 49b7e63..08aad3e 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -411,9 +411,6 @@ struct CPUMIPSState {
int32_t CP0_DESAVE;
/* Qemu */
int interrupt_request;
- jmp_buf jmp_env;
- int exception_index;
- int error_code;
int user_mode_only; /* user mode only simulation */
uint32_t hflags; /* CPU State */
/* TMASK defines different execution modes */
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 7f7916f..e9f9287 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -648,8 +648,6 @@ struct CPUPPCState {
int bfd_mach;
uint32_t flags;
- int exception_index;
- int error_code;
int interrupt_request;
uint32_t pending_interrupts;
#if !defined(CONFIG_USER_ONLY)
@@ -674,7 +672,6 @@ struct CPUPPCState {
opc_handler_t *opcodes[0x40];
/* Those resources are used only in Qemu core */
- jmp_buf jmp_env;
int user_mode_only; /* user mode only simulation */
target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 72ac82f..534ada3 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -114,11 +114,9 @@ typedef struct CPUSH4State {
uint32_t expevt; /* exception event register */
uint32_t intevt; /* interrupt event register */
- jmp_buf jmp_env;
int user_mode_only;
int interrupt_request;
int halted;
- int exception_index;
CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */
tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
void *intc_handle;
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index af0ebd1..b663fe2 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -214,9 +214,7 @@ typedef struct CPUSPARCState {
uint32_t pil_in; /* incoming interrupt level bitmap */
int psref; /* enable fpu */
target_ulong version;
- jmp_buf jmp_env;
int user_mode_only;
- int exception_index;
int interrupt_index;
int interrupt_request;
int halted;
--
1.5.4.5
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Qemu-devel] [PATCH 3/3] use halted attribute for i386 too.
2008-05-21 21:40 ` [Qemu-devel] [PATCH 2/3] Push common interrupt variables to cpu-defs.h Glauber Costa
@ 2008-05-21 21:40 ` Glauber Costa
2008-05-21 22:08 ` [Qemu-devel] " Anthony Liguori
0 siblings, 1 reply; 4+ messages in thread
From: Glauber Costa @ 2008-05-21 21:40 UTC (permalink / raw)
To: qemu-devel; +Cc: kvm-devel
Unlike other architectures, i386 lacked a "halted" attribute, going
with a flag into hflags. By using the halted attribute, we can make
the code look like more other architectures, and simplify the code in
some instances. In this commit, we make the code for info_cpus simpler
in monitor.c
Signed-off-by: Glauber Costa <gcosta@redhat.com>
---
cpu-defs.h | 2 ++
exec-all.h | 1 +
hw/apic.c | 4 ++--
hw/pc.c | 2 +-
monitor.c | 23 +++++------------------
target-alpha/cpu.h | 1 -
target-alpha/helper.c | 1 +
target-arm/cpu.h | 1 -
target-arm/helper.c | 1 +
target-cris/cpu.h | 1 -
target-cris/helper.c | 1 +
target-i386/exec.h | 4 ++--
target-i386/helper.c | 9 ++++++++-
target-m68k/cpu.h | 1 -
target-m68k/helper.c | 1 +
target-mips/cpu.h | 2 --
target-mips/helper.c | 5 +++++
target-ppc/cpu.h | 2 --
target-ppc/helper.c | 6 ++++++
target-sh4/cpu.h | 1 -
target-sh4/helper.c | 1 +
target-sparc/cpu.h | 1 -
target-sparc/helper.c | 5 +++++
23 files changed, 42 insertions(+), 34 deletions(-)
diff --git a/cpu-defs.h b/cpu-defs.h
index bb00c80..5bcd1ee 100644
--- a/cpu-defs.h
+++ b/cpu-defs.h
@@ -164,6 +164,8 @@ typedef struct CPUTLBEntry {
int exception_index; \
int error_code; \
\
+ int halted; \
+ \
void *next_cpu; /* next CPU sharing TB cache */ \
int cpu_index; /* CPU index (informative) */ \
/* user data */ \
diff --git a/exec-all.h b/exec-all.h
index ce0e839..3a98826 100644
--- a/exec-all.h
+++ b/exec-all.h
@@ -83,6 +83,7 @@ int cpu_restore_state_copy(struct TranslationBlock *tb,
void cpu_resume_from_signal(CPUState *env1, void *puc);
void cpu_exec_init(CPUState *env);
+extern int cpu_info_ip(CPUState *env, char *buf);
void cpu_pre_exec(CPUState *env);
void cpu_post_exec(CPUState *env);
diff --git a/hw/apic.c b/hw/apic.c
index a1ebf21..0dc9f8e 100644
--- a/hw/apic.c
+++ b/hw/apic.c
@@ -443,12 +443,12 @@ static void apic_init_ipi(APICState *s)
static void apic_startup(APICState *s, int vector_num)
{
CPUState *env = s->cpu_env;
- if (!(env->hflags & HF_HALTED_MASK))
+ if (!(env->halted))
return;
env->eip = 0;
cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
0xffff, 0);
- env->hflags &= ~HF_HALTED_MASK;
+ env->halted = 0;
}
static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
diff --git a/hw/pc.c b/hw/pc.c
index c92384c..c68323b 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -761,7 +761,7 @@ static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
exit(1);
}
if (i != 0)
- env->hflags |= HF_HALTED_MASK;
+ env->halted = 1;
if (smp_cpus > 1) {
/* XXX: enable it in all cases */
env->cpuid_features |= CPUID_APIC;
diff --git a/monitor.c b/monitor.c
index 236b827..f34d147 100644
--- a/monitor.c
+++ b/monitor.c
@@ -36,6 +36,8 @@
#include "disas.h"
#include <dirent.h>
+#include "exec-all.h"
+
#ifdef CONFIG_PROFILER
#include "qemu-timer.h" /* for ticks_per_sec */
#endif
@@ -304,6 +306,7 @@ static void do_info_registers(void)
static void do_info_cpus(void)
{
CPUState *env;
+ char buf[1024];
/* just to set the default cpu if not already done */
mon_get_cpu();
@@ -312,24 +315,8 @@ static void do_info_cpus(void)
term_printf("%c CPU #%d:",
(env == mon_cpu) ? '*' : ' ',
env->cpu_index);
-#if defined(TARGET_I386)
- term_printf(" pc=0x" TARGET_FMT_lx, env->eip + env->segs[R_CS].base);
- if (env->hflags & HF_HALTED_MASK)
- term_printf(" (halted)");
-#elif defined(TARGET_PPC)
- term_printf(" nip=0x" TARGET_FMT_lx, env->nip);
- if (env->halted)
- term_printf(" (halted)");
-#elif defined(TARGET_SPARC)
- term_printf(" pc=0x" TARGET_FMT_lx " npc=0x" TARGET_FMT_lx, env->pc, env->npc);
- if (env->halted)
- term_printf(" (halted)");
-#elif defined(TARGET_MIPS)
- term_printf(" PC=0x" TARGET_FMT_lx, env->PC[env->current_tc]);
- if (env->halted)
- term_printf(" (halted)");
-#endif
- term_printf("\n");
+ if (cpu_info_ip(env, buf))
+ term_printf("%s %s\n", buf, env->halted ? "(halted)" : "");
}
}
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index b3c10d7..dc2460a 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -284,7 +284,6 @@ struct CPUAlphaState {
int user_mode_only; /* user mode only simulation */
uint32_t hflags;
- int halted;
int interrupt_request;
diff --git a/target-alpha/helper.c b/target-alpha/helper.c
index 73d565f..6056d6c 100644
--- a/target-alpha/helper.c
+++ b/target-alpha/helper.c
@@ -453,5 +453,6 @@ void cpu_dump_EA (target_ulong EA)
fprintf(f, "Memory access at address " TARGET_FMT_lx "\n", EA);
}
+int cpu_info_ip(CPUState *env, char *buf) { return 0; }
void cpu_pre_exec(CPUState *env) {}
void cpu_post_exec(CPUState *env) {}
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 60a7a64..8d0558c 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -158,7 +158,6 @@ typedef struct CPUARMState {
/* exception/interrupt handling */
int interrupt_request;
int user_mode_only;
- int halted;
/* VFP coprocessor state. */
struct {
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 496f326..6724909 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2523,6 +2523,7 @@ uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env)
return float32_to_int32(tmp, s);
}
+int cpu_info_ip(CPUState *env, char *buf) { return 0; }
void cpu_pre_exec(CPUState *env) { }
/* XXX: Save/restore host fpu exception state?. */
void cpu_post_exec(CPUState *env) { }
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index d45abea..acc1b5d 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -161,7 +161,6 @@ typedef struct CPUCRISState {
int features;
int user_mode_only;
- int halted;
CPU_COMMON
} CPUCRISState;
diff --git a/target-cris/helper.c b/target-cris/helper.c
index 1e216aa..0ed169c 100644
--- a/target-cris/helper.c
+++ b/target-cris/helper.c
@@ -184,5 +184,6 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
}
#endif
+int cpu_info_ip(CPUState *env, char *buf) { return 0; }
void cpu_pre_exec(CPUState *env) {}
void cpu_post_exec(CPUState *env) {}
diff --git a/target-i386/exec.h b/target-i386/exec.h
index 8597e79..f6517ce 100644
--- a/target-i386/exec.h
+++ b/target-i386/exec.h
@@ -425,13 +425,13 @@ static inline void regs_to_env(void)
static inline int cpu_halted(CPUState *env) {
/* handle exit of HALTED state */
- if (!(env->hflags & HF_HALTED_MASK))
+ if (!(env->halted))
return 0;
/* disable halt condition */
if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
(env->eflags & IF_MASK)) ||
(env->interrupt_request & CPU_INTERRUPT_NMI)) {
- env->hflags &= ~HF_HALTED_MASK;
+ env->halted = 0;
return 0;
}
return EXCP_HALTED;
diff --git a/target-i386/helper.c b/target-i386/helper.c
index e8809c2..9d5c3de 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -4511,7 +4511,7 @@ void helper_idivq_EAX(target_ulong t0)
void helper_hlt(void)
{
env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
- env->hflags |= HF_HALTED_MASK;
+ env->halted = 1;
env->exception_index = EXCP_HLT;
cpu_loop_exit();
}
@@ -4692,6 +4692,13 @@ void helper_clgi(void)
{
env->hflags &= ~HF_GIF_MASK;
}
+
+int cpu_info_ip(CPUState *env, char *buf)
+{
+ sprintf(buf, " pc=0x" TARGET_FMT_lx, env->eip + env->segs[R_CS].base);
+ return 1;
+}
+
void cpu_pre_exec(CPUState *env)
{
/* put eflags in CPU temporary format */
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index ba36387..e8c1dfc 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -106,7 +106,6 @@ typedef struct CPUM68KState {
/* exception/interrupt handling */
int interrupt_request;
int user_mode_only;
- int halted;
int pending_vector;
int pending_level;
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 73e93bc..82b5576 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -339,6 +339,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
return addr;
}
+int cpu_info_ip(CPUState *env, char *buf) { return 0; }
void cpu_pre_exec(CPUState *env)
{
env->cc_op = CC_OP_FLAGS;
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 08aad3e..38ae0b4 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -445,8 +445,6 @@ struct CPUMIPSState {
target_ulong btarget; /* Jump / branch target */
int bcond; /* Branch condition (if needed) */
- int halted; /* TRUE if the CPU is in suspend state */
-
int SYNCI_Step; /* Address step size for SYNCI */
int CCRes; /* Cycle count resolution/divisor */
uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 90e6dbe..1499be2 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -637,5 +637,10 @@ void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
}
}
+int cpu_info_ip(CPUState *env, char *buf)
+{
+ sprintf(buf, " PC=0x" TARGET_FMT_lx, env->PC[env->current_tc]);
+}
+
void cpu_post_exec(CPUState *env) { }
void cpu_pre_exec(CPUState *env) { }
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index e9f9287..a1f90e2 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -586,8 +586,6 @@ struct CPUPPCState {
CPU_COMMON
- int halted; /* TRUE if the CPU is in suspend state */
-
int access_type; /* when a memory exception occurs, the access
type is stored here */
diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index 300532f..2858780 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -2989,5 +2989,11 @@ void cpu_ppc_close (CPUPPCState *env)
qemu_free(env);
}
+int cpu_info_ip(CPUState *env, char *buf)
+{
+ sprintf(buf, " nip=0x" TARGET_FMT_lx, env->nip);
+ return 1;
+}
+
void cpu_pre_exec(CPUState *env) { }
void cpu_post_exec(CPUState *env) { }
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 534ada3..c03cdb1 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -116,7 +116,6 @@ typedef struct CPUSH4State {
int user_mode_only;
int interrupt_request;
- int halted;
CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */
tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
void *intc_handle;
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index ebc16ac..df64d28 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -535,5 +535,6 @@ void cpu_load_tlb(CPUState * env)
#endif
+int cpu_info_ip(CPUState *env, char *buf) { return 0; }
void cpu_pre_exec(CPUState *env) {}
void cpu_post_exec(CPUState *env) {}
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index b663fe2..ba3ee01 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -217,7 +217,6 @@ typedef struct CPUSPARCState {
int user_mode_only;
int interrupt_index;
int interrupt_request;
- int halted;
uint32_t mmu_bm;
uint32_t mmu_ctpr_mask;
uint32_t mmu_cxr_mask;
diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index 76c68fa..2f887f1 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -1320,6 +1320,11 @@ void cpu_dump_state(CPUState *env, FILE *f,
static uint32_t *saved_regwptr;
#endif
+int cpu_info_ip(CPUState *env, char *buf)
+{
+ term_printf(" pc=0x" TARGET_FMT_lx " npc=0x" TARGET_FMT_lx, env->pc, env->npc);
+}
+
void cpu_pre_exec(CPUState *env)
{
#if defined(reg_REGWPTR)
--
1.5.4.5
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Qemu-devel] Re: [PATCH 3/3] use halted attribute for i386 too.
2008-05-21 21:40 ` [Qemu-devel] [PATCH 3/3] use halted attribute for i386 too Glauber Costa
@ 2008-05-21 22:08 ` Anthony Liguori
0 siblings, 0 replies; 4+ messages in thread
From: Anthony Liguori @ 2008-05-21 22:08 UTC (permalink / raw)
To: Glauber Costa; +Cc: kvm-devel, qemu-devel
Glauber Costa wrote:
> Unlike other architectures, i386 lacked a "halted" attribute, going
> with a flag into hflags. By using the halted attribute, we can make
> the code look like more other architectures, and simplify the code in
> some instances. In this commit, we make the code for info_cpus simpler
> in monitor.c
>
In the future, it would be better not to include both the halted change
and the IP accessor in the same function. Plus, I'm not sure that
accessor really should be doing the formating. eip will always be of
type target_ulong so it just needs a #define for the printf formating
(which is what the code does today).
Regards,
Anthony Liguori
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2008-05-21 22:09 UTC | newest]
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2008-05-21 21:40 [Qemu-devel] [PATCH 0/2] use halted attribute for x86 Glauber Costa
2008-05-21 21:40 ` [Qemu-devel] [PATCH 2/3] Push common interrupt variables to cpu-defs.h Glauber Costa
2008-05-21 21:40 ` [Qemu-devel] [PATCH 3/3] use halted attribute for i386 too Glauber Costa
2008-05-21 22:08 ` [Qemu-devel] " Anthony Liguori
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