From: Amit Shah <amit.shah@qumranet.com>
To: qemu-devel@nongnu.org
Cc: Amit Shah <amit.shah@qumranet.com>, kvm@vger.kernel.org
Subject: [Qemu-devel] [PATCH 09/14] QEMU: Fill in PCI subsystem vendor id for piix_pci
Date: Mon, 26 May 2008 13:36:48 +0300 [thread overview]
Message-ID: <1211798213-4187-12-git-send-email-amit.shah@qumranet.com> (raw)
In-Reply-To: <1211798213-4187-11-git-send-email-amit.shah@qumranet.com>
The subsystem vendor ID shouldn't be 0x0 or 0xffff according
to the PCI spec
Signed-off-by: Amit Shah <amit.shah@qumranet.com>
---
qemu/hw/piix_pci.c | 12 ++++++------
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/qemu/hw/piix_pci.c b/qemu/hw/piix_pci.c
index 90cb3a6..ac3c3fc 100644
--- a/qemu/hw/piix_pci.c
+++ b/qemu/hw/piix_pci.c
@@ -192,8 +192,8 @@ PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic)
d = pci_register_device(b, "i440FX", sizeof(PCIDevice), 0,
NULL, i440fx_write_config);
- d->config[0x00] = 0x86; // vendor_id
- d->config[0x01] = 0x80;
+ d->config[0x00] = d->config[0x2c] = 0x86; // vendor_id
+ d->config[0x01] = d->config[0x2d] = 0x80;
d->config[0x02] = 0x37; // device_id
d->config[0x03] = 0x12;
d->config[0x08] = 0x02; // revision
@@ -337,8 +337,8 @@ int piix3_init(PCIBus *bus, int devfn)
piix3_dev = d;
pci_conf = d->config;
- pci_conf[0x00] = 0x86; // Intel
- pci_conf[0x01] = 0x80;
+ pci_conf[0x00] = pci_conf[0x2c] = 0x86; // Intel
+ pci_conf[0x01] = pci_conf[0x2d] = 0x80;
pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
pci_conf[0x03] = 0x70;
pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
@@ -361,8 +361,8 @@ int piix4_init(PCIBus *bus, int devfn)
piix4_dev = d;
pci_conf = d->config;
- pci_conf[0x00] = 0x86; // Intel
- pci_conf[0x01] = 0x80;
+ pci_conf[0x00] = pci_conf[0x2c] = 0x86; // Intel
+ pci_conf[0x01] = pci_conf[0x2d] = 0x80;
pci_conf[0x02] = 0x10; // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge
pci_conf[0x03] = 0x71;
pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
--
1.5.5.1
next prev parent reply other threads:[~2008-05-26 10:37 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-05-26 10:36 [Qemu-devel] PCI: Add subsystem vendor IDs and mask writes to RO bits Amit Shah
2008-05-26 10:36 ` [Qemu-devel] [PATCH 01/14] QEMU: Fill in PCI subsystem vendor id for acpi Amit Shah
2008-05-26 10:36 ` [Qemu-devel] [PATCH 1/2] QEMU: Mask writes to RO bits in the status reg of PCI config space Amit Shah
2008-05-26 10:36 ` [Qemu-devel] [PATCH 02/14] QEMU: Fill in PCI subsystem vendor id for cirrus_vga Amit Shah
2008-05-26 10:36 ` [Qemu-devel] [PATCH 2/2] QEMU: Mask writes to RO bits in the command reg of PCI config space Amit Shah
2008-05-26 10:36 ` [Qemu-devel] [PATCH 03/14] QEMU: Fill in PCI subsystem vendor id for e1000 Amit Shah
2008-05-26 10:36 ` [Qemu-devel] [PATCH 04/14] QEMU: Fill in PCI subsystem vendor id for eepro100 Amit Shah
2008-05-26 10:36 ` [Qemu-devel] [PATCH 05/14] QEMU: Fill in PCI subsystem vendor id for ide Amit Shah
2008-05-26 10:36 ` [Qemu-devel] [PATCH 06/14] QEMU: Fill in PCI subsystem vendor id for LSI Amit Shah
2008-05-26 10:36 ` [Qemu-devel] [PATCH 07/14] QEMU: Fill in PCI subsystem vendor id for ne2000 Amit Shah
2008-05-26 10:36 ` [Qemu-devel] [PATCH 08/14] QEMU: Fill in PCI subsystem vendor id for pcnet Amit Shah
2008-05-26 10:36 ` Amit Shah [this message]
2008-05-26 10:36 ` [Qemu-devel] [PATCH 10/14] QEMU: Fill in PCI subsystem vendor id for rtl8139 Amit Shah
2008-05-26 10:36 ` [Qemu-devel] [PATCH 11/14] QEMU: Fill in PCI subsystem vendor id for usb-ohci Amit Shah
2008-05-26 10:36 ` [Qemu-devel] [PATCH 12/14] QEMU: Fill in PCI subsystem vendor id for usb-uhci Amit Shah
2008-05-26 10:36 ` [Qemu-devel] [PATCH 13/14] QEMU: Fill in PCI subsystem vendor id for versatile_pci Amit Shah
2008-05-26 10:36 ` [Qemu-devel] [PATCH 14/14] QEMU: Fill in PCI subsystem vendor id for vga Amit Shah
2008-05-26 18:36 ` [Qemu-devel] [PATCH 03/14] QEMU: Fill in PCI subsystem vendor id for e1000 M. Warner Losh
2008-05-27 15:01 ` Amit Shah
2008-05-26 18:33 ` [Qemu-devel] [PATCH 1/2] QEMU: Mask writes to RO bits in the status reg of PCI config space M. Warner Losh
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