[Qemu-devel] PCI: Add subsystem vendor IDs and mask writes to RO bits

[Qemu-devel] PCI: Add subsystem vendor IDs and mask writes to RO bits

[Amit Shah]

[Qemu-devel] [PATCH 01/14] QEMU: Fill in PCI subsystem vendor id for acpi

[Amit Shah]

The subsystem vendor ID shouldn't be 0x0 or 0xffff according
to the PCI spec

Signed-off-by: Amit Shah <amit.shah@qumranet.com>
---
 qemu/hw/acpi.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/qemu/hw/acpi.c b/qemu/hw/acpi.c
index c305702..1ab031a 100644
--- a/qemu/hw/acpi.c
+++ b/qemu/hw/acpi.c
@@ -486,8 +486,8 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                                          devfn, NULL, pm_write_config);
     pm_state = s;
     pci_conf = s->dev.config;
-    pci_conf[0x00] = 0x86;
-    pci_conf[0x01] = 0x80;
+    pci_conf[0x00] = pci_conf[0x2c] = 0x86;
+    pci_conf[0x01] = pci_conf[0x2d] = 0x80;
     pci_conf[0x02] = 0x13;
     pci_conf[0x03] = 0x71;
     pci_conf[0x06] = 0x80;
-- 
1.5.5.1

[Qemu-devel] [PATCH 1/2] QEMU: Mask writes to RO bits in the status reg of PCI config space

[Amit Shah]

The Status register in the PCI config space has some read-only bits.
Any writes to those bits should be masked out.

Signed-off-by: Amit Shah <amit.shah@qumranet.com>
---
 qemu/hw/pci.c |   11 +++++++++++
 qemu/hw/pci.h |   15 +++++++++++++++
 2 files changed, 26 insertions(+), 0 deletions(-)

diff --git a/qemu/hw/pci.c b/qemu/hw/pci.c
index a23a466..6916f4a 100644
--- a/qemu/hw/pci.c
+++ b/qemu/hw/pci.c
@@ -410,6 +410,7 @@ void pci_default_write_config(PCIDevice *d,
             case 0x0b:
             case 0x0e:
             case 0x10 ... 0x27: /* base */
+            case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
             case 0x30 ... 0x33: /* rom */
             case 0x3d:
                 can_write = 0;
@@ -431,6 +432,7 @@ void pci_default_write_config(PCIDevice *d,
             case 0x0a:
             case 0x0b:
             case 0x0e:
+            case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
             case 0x38 ... 0x3b: /* rom */
             case 0x3d:
                 can_write = 0;
@@ -442,6 +444,15 @@ void pci_default_write_config(PCIDevice *d,
             break;
         }
         if (can_write) {
+            /* Mask out writes to reserved bits in registers */
+            switch (addr) {
+            case 0x06:
+                val &= ~PCI_STATUS_RESERVED_MASK_LO;
+                break;
+            case 0x07:
+                val &= ~PCI_STATUS_RESERVED_MASK_HI;
+                break;
+            }
             d->config[addr] = val;
         }
         if (++addr > 0xff)
diff --git a/qemu/hw/pci.h b/qemu/hw/pci.h
index 60e4094..a0cbdd5 100644
--- a/qemu/hw/pci.h
+++ b/qemu/hw/pci.h
@@ -46,6 +46,21 @@ typedef struct PCIIORegion {
 #define PCI_MIN_GNT		0x3e	/* 8 bits */
 #define PCI_MAX_LAT		0x3f	/* 8 bits */
 
+/* Bits in the PCI Status Register (PCI 2.3 spec) */
+#define PCI_STATUS_RESERVED1	0x007
+#define PCI_STATUS_INT_STATUS	0x008
+#define PCI_STATUS_CAPABILITIES	0x010
+#define PCI_STATUS_66MHZ	0x020
+#define PCI_STATUS_RESERVED2	0x040
+#define PCI_STATUS_FAST_BACK	0x080
+#define PCI_STATUS_DEVSEL	0x600
+
+#define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
+                PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
+                PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK)
+
+#define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
+
 struct PCIDevice {
     /* PCI config space */
     uint8_t config[256];
-- 
1.5.5.1

[Qemu-devel] [PATCH 02/14] QEMU: Fill in PCI subsystem vendor id for cirrus_vga

[Amit Shah]

The subsystem vendor ID shouldn't be 0x0 or 0xffff according
to the PCI spec

Signed-off-by: Amit Shah <amit.shah@qumranet.com>
---
 qemu/hw/cirrus_vga.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/qemu/hw/cirrus_vga.c b/qemu/hw/cirrus_vga.c
index 2c4aeec..21b4819 100644
--- a/qemu/hw/cirrus_vga.c
+++ b/qemu/hw/cirrus_vga.c
@@ -3425,8 +3425,8 @@ void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
                                                  sizeof(PCICirrusVGAState),
                                                  -1, NULL, NULL);
     pci_conf = d->dev.config;
-    pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff);
-    pci_conf[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8);
+    pci_conf[0x00] = pci_conf[0x2c] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff);
+    pci_conf[0x01] = pci_conf[0x2d] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8);
     pci_conf[0x02] = (uint8_t) (device_id & 0xff);
     pci_conf[0x03] = (uint8_t) (device_id >> 8);
     pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
-- 
1.5.5.1

[Qemu-devel] [PATCH 2/2] QEMU: Mask writes to RO bits in the command reg of PCI config space

[Amit Shah]

The Command register in the PCI config space has some read-only bits.
Any writes to those bits should be masked out.

Signed-off-by: Amit Shah <amit.shah@qumranet.com>
---
 qemu/hw/pci.c |    3 +++
 qemu/hw/pci.h |    5 +++++
 2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/qemu/hw/pci.c b/qemu/hw/pci.c
index 6916f4a..97dc54d 100644
--- a/qemu/hw/pci.c
+++ b/qemu/hw/pci.c
@@ -446,6 +446,9 @@ void pci_default_write_config(PCIDevice *d,
         if (can_write) {
             /* Mask out writes to reserved bits in registers */
             switch (addr) {
+	    case 0x05:
+                val &= ~PCI_COMMAND_RESERVED_MASK_HI;
+                break;
             case 0x06:
                 val &= ~PCI_STATUS_RESERVED_MASK_LO;
                 break;
diff --git a/qemu/hw/pci.h b/qemu/hw/pci.h
index a0cbdd5..f32b591 100644
--- a/qemu/hw/pci.h
+++ b/qemu/hw/pci.h
@@ -61,6 +61,11 @@ typedef struct PCIIORegion {
 
 #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
 
+/* Bits in the PCI Command Register (PCI 2.3 spec) */
+#define PCI_COMMAND_RESERVED	0xf800
+
+#define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
+
 struct PCIDevice {
     /* PCI config space */
     uint8_t config[256];
-- 
1.5.5.1

[Qemu-devel] [PATCH 03/14] QEMU: Fill in PCI subsystem vendor id for e1000

[Amit Shah]

The subsystem vendor ID shouldn't be 0x0 or 0xffff according
to the PCI spec

Signed-off-by: Amit Shah <amit.shah@qumranet.com>
---
 qemu/hw/e1000.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/qemu/hw/e1000.c b/qemu/hw/e1000.c
index 01f8983..bda6b5e 100644
--- a/qemu/hw/e1000.c
+++ b/qemu/hw/e1000.c
@@ -977,6 +977,7 @@ pci_e1000_init(PCIBus *bus, NICInfo *nd, int devfn)
     pci_conf[0x0a] = 0x00; // ethernet network controller
     pci_conf[0x0b] = 0x02;
     pci_conf[0x0c] = 0x10;
+    *(uint16_t *)(pci_conf+0x2c) = cpu_to_le16(0x8086);
 
     pci_conf[0x3d] = 1; // interrupt pin 0
 
-- 
1.5.5.1

[Qemu-devel] [PATCH 04/14] QEMU: Fill in PCI subsystem vendor id for eepro100

[Amit Shah]

The subsystem vendor ID shouldn't be 0x0 or 0xffff according
to the PCI spec

Signed-off-by: Amit Shah <amit.shah@qumranet.com>
---
 qemu/hw/eepro100.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/qemu/hw/eepro100.c b/qemu/hw/eepro100.c
index ccb5f8b..b49b774 100644
--- a/qemu/hw/eepro100.c
+++ b/qemu/hw/eepro100.c
@@ -64,6 +64,8 @@
 #define PCI_BASE_ADDRESS_4      0x20    /* 32 bits */
 #define PCI_BASE_ADDRESS_5      0x24    /* 32 bits */
 
+#define PCI_SUBSYSTEM_VENDOR_ID 0x2c    /* 16 bits */
+
 #define PCI_CONFIG_8(offset, value) \
     (pci_conf[offset] = (value))
 #define PCI_CONFIG_16(offset, value) \
@@ -423,6 +425,7 @@ static void pci_reset(EEPRO100State * s)
 
     /* PCI Vendor ID */
     PCI_CONFIG_16(PCI_VENDOR_ID, 0x8086);
+    PCI_CONFIG_16(PCI_SUBSYSTEM_VENDOR_ID, 0x8086);
     /* PCI Device ID */
     PCI_CONFIG_16(PCI_DEVICE_ID, 0x1209);
     /* PCI Command */
-- 
1.5.5.1

[Qemu-devel] [PATCH 05/14] QEMU: Fill in PCI subsystem vendor id for ide

[Amit Shah]

The subsystem vendor ID shouldn't be 0x0 or 0xffff according
to the PCI spec

Signed-off-by: Amit Shah <amit.shah@qumranet.com>
---
 qemu/hw/ide.c |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/qemu/hw/ide.c b/qemu/hw/ide.c
index 69363a9..d3e0ef6 100644
--- a/qemu/hw/ide.c
+++ b/qemu/hw/ide.c
@@ -2874,8 +2874,8 @@ void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
                                            NULL, NULL);
     d->type = IDE_TYPE_CMD646;
     pci_conf = d->dev.config;
-    pci_conf[0x00] = 0x95; // CMD646
-    pci_conf[0x01] = 0x10;
+    pci_conf[0x00] = pci_conf[0x2c] = 0x95; // CMD646
+    pci_conf[0x01] = pci_conf[0x2d] = 0x10;
     pci_conf[0x02] = 0x46;
     pci_conf[0x03] = 0x06;
 
@@ -3005,8 +3005,8 @@ void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
     d->type = IDE_TYPE_PIIX3;
 
     pci_conf = d->dev.config;
-    pci_conf[0x00] = 0x86; // Intel
-    pci_conf[0x01] = 0x80;
+    pci_conf[0x00] = pci_conf[0x2c] = 0x86; // Intel
+    pci_conf[0x01] = pci_conf[0x2d] = 0x80;
     pci_conf[0x02] = 0x10;
     pci_conf[0x03] = 0x70;
     pci_conf[0x09] = 0x80; // legacy ATA mode
@@ -3047,8 +3047,8 @@ void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
     d->type = IDE_TYPE_PIIX4;
 
     pci_conf = d->dev.config;
-    pci_conf[0x00] = 0x86; // Intel
-    pci_conf[0x01] = 0x80;
+    pci_conf[0x00] = pci_conf[0x2c] = 0x86; // Intel
+    pci_conf[0x01] = pci_conf[0x2d] = 0x80;
     pci_conf[0x02] = 0x11;
     pci_conf[0x03] = 0x71;
     pci_conf[0x09] = 0x80; // legacy ATA mode
-- 
1.5.5.1

[Qemu-devel] [PATCH 06/14] QEMU: Fill in PCI subsystem vendor id for LSI

[Amit Shah]

The subsystem vendor ID shouldn't be 0x0 or 0xffff according
to the PCI spec

Signed-off-by: Amit Shah <amit.shah@qumranet.com>
---
 qemu/hw/lsi53c895a.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/qemu/hw/lsi53c895a.c b/qemu/hw/lsi53c895a.c
index 72ed5c3..5e71e15 100644
--- a/qemu/hw/lsi53c895a.c
+++ b/qemu/hw/lsi53c895a.c
@@ -1872,8 +1872,8 @@ void *lsi_scsi_init(PCIBus *bus, int devfn)
         return NULL;
     }
 
-    s->pci_dev.config[0x00] = 0x00;
-    s->pci_dev.config[0x01] = 0x10;
+    s->pci_dev.config[0x00] = s->pci_dev.config[0x2c] = 0x00;
+    s->pci_dev.config[0x01] = s->pci_dev.config[0x2d] = 0x10;
     s->pci_dev.config[0x02] = 0x12;
     s->pci_dev.config[0x03] = 0x00;
     s->pci_dev.config[0x0b] = 0x01;
-- 
1.5.5.1

[Qemu-devel] [PATCH 07/14] QEMU: Fill in PCI subsystem vendor id for ne2000

[Amit Shah]

The subsystem vendor ID shouldn't be 0x0 or 0xffff according
to the PCI spec

Signed-off-by: Amit Shah <amit.shah@qumranet.com>
---
 qemu/hw/ne2000.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/qemu/hw/ne2000.c b/qemu/hw/ne2000.c
index ddc59b5..9ba775d 100644
--- a/qemu/hw/ne2000.c
+++ b/qemu/hw/ne2000.c
@@ -800,8 +800,8 @@ PCIDevice *pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn)
        return NULL;
 
     pci_conf = d->dev.config;
-    pci_conf[0x00] = 0xec; // Realtek 8029
-    pci_conf[0x01] = 0x10;
+    pci_conf[0x00] = pci_conf[0x2c] = 0xec; // Realtek 8029
+    pci_conf[0x01] = pci_conf[0x2d] = 0x10;
     pci_conf[0x02] = 0x29;
     pci_conf[0x03] = 0x80;
     pci_conf[0x0a] = 0x00; // ethernet network controller
-- 
1.5.5.1

[Qemu-devel] [PATCH 08/14] QEMU: Fill in PCI subsystem vendor id for pcnet

[Amit Shah]

The subsystem vendor ID shouldn't be 0x0 or 0xffff according
to the PCI spec

Signed-off-by: Amit Shah <amit.shah@qumranet.com>
---
 qemu/hw/pcnet.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/qemu/hw/pcnet.c b/qemu/hw/pcnet.c
index a1fb610..1bbd626 100644
--- a/qemu/hw/pcnet.c
+++ b/qemu/hw/pcnet.c
@@ -1975,6 +1975,7 @@ PCIDevice *pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn)
     pci_conf = d->dev.config;
 
     *(uint16_t *)&pci_conf[0x00] = cpu_to_le16(0x1022);
+    *(uint16_t *)&pci_conf[0x2c] = cpu_to_le16(0x1022);
     *(uint16_t *)&pci_conf[0x02] = cpu_to_le16(0x2000);
     *(uint16_t *)&pci_conf[0x04] = cpu_to_le16(0x0007);
     *(uint16_t *)&pci_conf[0x06] = cpu_to_le16(0x0280);
-- 
1.5.5.1

[Qemu-devel] [PATCH 09/14] QEMU: Fill in PCI subsystem vendor id for piix_pci

[Amit Shah]

The subsystem vendor ID shouldn't be 0x0 or 0xffff according
to the PCI spec

Signed-off-by: Amit Shah <amit.shah@qumranet.com>
---
 qemu/hw/piix_pci.c |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/qemu/hw/piix_pci.c b/qemu/hw/piix_pci.c
index 90cb3a6..ac3c3fc 100644
--- a/qemu/hw/piix_pci.c
+++ b/qemu/hw/piix_pci.c
@@ -192,8 +192,8 @@ PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic)
     d = pci_register_device(b, "i440FX", sizeof(PCIDevice), 0,
                             NULL, i440fx_write_config);
 
-    d->config[0x00] = 0x86; // vendor_id
-    d->config[0x01] = 0x80;
+    d->config[0x00] = d->config[0x2c] = 0x86; // vendor_id
+    d->config[0x01] = d->config[0x2d] = 0x80;
     d->config[0x02] = 0x37; // device_id
     d->config[0x03] = 0x12;
     d->config[0x08] = 0x02; // revision
@@ -337,8 +337,8 @@ int piix3_init(PCIBus *bus, int devfn)
     piix3_dev = d;
     pci_conf = d->config;
 
-    pci_conf[0x00] = 0x86; // Intel
-    pci_conf[0x01] = 0x80;
+    pci_conf[0x00] = pci_conf[0x2c] = 0x86; // Intel
+    pci_conf[0x01] = pci_conf[0x2d] = 0x80;
     pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
     pci_conf[0x03] = 0x70;
     pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
@@ -361,8 +361,8 @@ int piix4_init(PCIBus *bus, int devfn)
     piix4_dev = d;
     pci_conf = d->config;
 
-    pci_conf[0x00] = 0x86; // Intel
-    pci_conf[0x01] = 0x80;
+    pci_conf[0x00] = pci_conf[0x2c] = 0x86; // Intel
+    pci_conf[0x01] = pci_conf[0x2d] = 0x80;
     pci_conf[0x02] = 0x10; // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge
     pci_conf[0x03] = 0x71;
     pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
-- 
1.5.5.1

[Qemu-devel] [PATCH 10/14] QEMU: Fill in PCI subsystem vendor id for rtl8139

[Amit Shah]

The subsystem vendor ID shouldn't be 0x0 or 0xffff according
to the PCI spec

Signed-off-by: Amit Shah <amit.shah@qumranet.com>
---
 qemu/hw/rtl8139.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/qemu/hw/rtl8139.c b/qemu/hw/rtl8139.c
index e4df58f..56ed9c7 100644
--- a/qemu/hw/rtl8139.c
+++ b/qemu/hw/rtl8139.c
@@ -3415,8 +3415,8 @@ PCIDevice *pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn)
 	return NULL;
 
     pci_conf = d->dev.config;
-    pci_conf[0x00] = 0xec; /* Realtek 8139 */
-    pci_conf[0x01] = 0x10;
+    pci_conf[0x00] = pci_conf[0x2c] = 0xec; /* Realtek 8139 */
+    pci_conf[0x01] = pci_conf[0x2d] = 0x10;
     pci_conf[0x02] = 0x39;
     pci_conf[0x03] = 0x81;
     pci_conf[0x04] = 0x05; /* command = I/O space, Bus Master */
-- 
1.5.5.1

[Qemu-devel] [PATCH 11/14] QEMU: Fill in PCI subsystem vendor id for usb-ohci

[Amit Shah]

The subsystem vendor ID shouldn't be 0x0 or 0xffff according
to the PCI spec

Signed-off-by: Amit Shah <amit.shah@qumranet.com>
---
 qemu/hw/usb-ohci.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/qemu/hw/usb-ohci.c b/qemu/hw/usb-ohci.c
index 68995b0..692d0ce 100644
--- a/qemu/hw/usb-ohci.c
+++ b/qemu/hw/usb-ohci.c
@@ -1655,8 +1655,8 @@ void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn)
         return;
     }
 
-    ohci->pci_dev.config[0x00] = vid & 0xff;
-    ohci->pci_dev.config[0x01] = (vid >> 8) & 0xff;
+    ohci->pci_dev.config[0x00] = ohci->pci_dev.config[0x2c] = vid & 0xff;
+    ohci->pci_dev.config[0x01] = ohci->pci_dev.config[0x2d] = (vid >> 8) & 0xff;
     ohci->pci_dev.config[0x02] = did & 0xff;
     ohci->pci_dev.config[0x03] = (did >> 8) & 0xff;
     ohci->pci_dev.config[0x09] = 0x10; /* OHCI */
-- 
1.5.5.1

[Qemu-devel] [PATCH 12/14] QEMU: Fill in PCI subsystem vendor id for usb-uhci

[Amit Shah]

The subsystem vendor ID shouldn't be 0x0 or 0xffff according
to the PCI spec

Signed-off-by: Amit Shah <amit.shah@qumranet.com>
---
 qemu/hw/usb-uhci.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/qemu/hw/usb-uhci.c b/qemu/hw/usb-uhci.c
index 12afade..7313a81 100644
--- a/qemu/hw/usb-uhci.c
+++ b/qemu/hw/usb-uhci.c
@@ -892,8 +892,8 @@ void usb_uhci_piix3_init(PCIBus *bus, int devfn)
                                         "USB-UHCI", sizeof(UHCIState),
                                         devfn, NULL, NULL);
     pci_conf = s->dev.config;
-    pci_conf[0x00] = 0x86;
-    pci_conf[0x01] = 0x80;
+    pci_conf[0x00] = pci_conf[0x2c] = 0x86;
+    pci_conf[0x01] = pci_conf[0x2d] = 0x80;
     pci_conf[0x02] = 0x20;
     pci_conf[0x03] = 0x70;
     pci_conf[0x08] = 0x01; // revision number
@@ -927,8 +927,8 @@ void usb_uhci_piix4_init(PCIBus *bus, int devfn)
                                         "USB-UHCI", sizeof(UHCIState),
                                         devfn, NULL, NULL);
     pci_conf = s->dev.config;
-    pci_conf[0x00] = 0x86;
-    pci_conf[0x01] = 0x80;
+    pci_conf[0x00] = pci_conf[0x2c] = 0x86;
+    pci_conf[0x01] = pci_conf[0x2d] = 0x80;
     pci_conf[0x02] = 0x12;
     pci_conf[0x03] = 0x71;
     pci_conf[0x08] = 0x01; // revision number
-- 
1.5.5.1

[Qemu-devel] [PATCH 13/14] QEMU: Fill in PCI subsystem vendor id for versatile_pci

[Amit Shah]

The subsystem vendor ID shouldn't be 0x0 or 0xffff according
to the PCI spec

Signed-off-by: Amit Shah <amit.shah@qumranet.com>
---
 qemu/hw/versatile_pci.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/qemu/hw/versatile_pci.c b/qemu/hw/versatile_pci.c
index 67cee88..d8aada1 100644
--- a/qemu/hw/versatile_pci.c
+++ b/qemu/hw/versatile_pci.c
@@ -124,8 +124,8 @@ PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview)
         isa_mmio_init(base + 0x03000000, 0x00100000);
     }
 
-    d->config[0x00] = 0xee; // vendor_id
-    d->config[0x01] = 0x10;
+    d->config[0x00] = d->config[0x2c] = 0xee; // vendor_id
+    d->config[0x01] = d->config[0x2d] = 0x10;
     /* Both boards have the same device ID.  Oh well.  */
     d->config[0x02] = 0x00; // device_id
     d->config[0x03] = 0x03;
-- 
1.5.5.1

[Qemu-devel] [PATCH 14/14] QEMU: Fill in PCI subsystem vendor id for vga

[Amit Shah]

The subsystem vendor ID shouldn't be 0x0 or 0xffff according
to the PCI spec

Signed-off-by: Amit Shah <amit.shah@qumranet.com>
---
 qemu/hw/vga.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/qemu/hw/vga.c b/qemu/hw/vga.c
index 3a49573..9bc867d 100644
--- a/qemu/hw/vga.c
+++ b/qemu/hw/vga.c
@@ -2406,8 +2406,8 @@ int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
     s->pci_dev = &d->dev;
 
     pci_conf = d->dev.config;
-    pci_conf[0x00] = 0x34; // dummy VGA (same as Bochs ID)
-    pci_conf[0x01] = 0x12;
+    pci_conf[0x00] = pci_conf[0x2c] = 0x34; // dummy VGA (same as Bochs ID)
+    pci_conf[0x01] = pci_conf[0x2d] = 0x12;
     pci_conf[0x02] = 0x11;
     pci_conf[0x03] = 0x11;
     pci_conf[0x0a] = 0x00; // VGA controller
-- 
1.5.5.1

Re: [Qemu-devel] [PATCH 03/14] QEMU: Fill in PCI subsystem vendor id for e1000

[M. Warner Losh]

Picking a random one to reply to:

In message: <1211798213-4187-6-git-send-email-amit.shah@qumranet.com>
            Amit Shah <amit.shah@qumranet.com> writes:
: The subsystem vendor ID shouldn't be 0x0 or 0xffff according
: to the PCI spec

Old versions of the spec allowed for these values.  Many older PCI
devices have 0xffff as their subvendor ID.  This is especially true
for video cards...

I'd be cautious in applying these patches, since QEMU tends to emulate
very old devices in some cases...

Warner

Re: [Qemu-devel] [PATCH 03/14] QEMU: Fill in PCI subsystem vendor id for e1000

[Amit Shah]

On Tuesday 27 May 2008 00:06:13 M. Warner Losh wrote:
> Picking a random one to reply to:
>
> In message: <1211798213-4187-6-git-send-email-amit.shah@qumranet.com>
>
>             Amit Shah <amit.shah@qumranet.com> writes:
> : The subsystem vendor ID shouldn't be 0x0 or 0xffff according
> : to the PCI spec
>
> Old versions of the spec allowed for these values.  Many older PCI
> devices have 0xffff as their subvendor ID.  This is especially true
> for video cards...

This is based on version 2.3 of the spec.

> I'd be cautious in applying these patches, since QEMU tends to emulate
> very old devices in some cases...

I would suggest applying the patches which have no objection and then 
reverting the ones which might cause such problems. We won't know who's using 
what unless this is done. That's the precise reason I've split them into so 
many patches.

Amit.

Re: [Qemu-devel] [PATCH 1/2] QEMU: Mask writes to RO bits in the status reg of PCI config space

[M. Warner Losh]

In message: <1211798213-4187-3-git-send-email-amit.shah@qumranet.com>
            Amit Shah <amit.shah@qumranet.com> writes:
: The Status register in the PCI config space has some read-only bits.
: Any writes to those bits should be masked out.

subvendor and subproduct aren't necessarily read-only.  There are
several devices that allow 'special magic' to enable their writing
(used by the BIOS).

Warner