From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1K1MEG-00026Z-Ik for qemu-devel@nongnu.org; Wed, 28 May 2008 10:02:12 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1K1MEF-00025o-Fe for qemu-devel@nongnu.org; Wed, 28 May 2008 10:02:11 -0400 Received: from [199.232.76.173] (port=55755 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1K1MEF-00025l-5p for qemu-devel@nongnu.org; Wed, 28 May 2008 10:02:11 -0400 Received: from mx1.redhat.com ([66.187.233.31]:33181) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1K1MEF-0001ai-46 for qemu-devel@nongnu.org; Wed, 28 May 2008 10:02:11 -0400 From: Glauber Costa Date: Wed, 28 May 2008 11:01:32 -0300 Message-Id: <1211983296-27395-3-git-send-email-gcosta@redhat.com> In-Reply-To: <1211983296-27395-2-git-send-email-gcosta@redhat.com> References: <1211983296-27395-1-git-send-email-gcosta@redhat.com> <1211983296-27395-2-git-send-email-gcosta@redhat.com> Subject: [Qemu-devel] [PATCH 2/6] simplify cpu_exec Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org This is a first attempt to simplify cpu_exec(): it has simply too many ifdefs, which is not a very good practice at all. Following some work I've already posted in the past, I'm moving the target-b ifdefs to target-xxx/helper.c, encapsuled into relevant functions. Signed-off-by: Glauber Costa --- cpu-exec.c | 43 ++----------------------------------------- exec-all.h | 10 ++++++++++ target-i386/exec.h | 15 +++++++++++++++ target-m68k/exec.h | 16 ++++++++++++++++ 4 files changed, 43 insertions(+), 41 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index 9b02447..af22e3c 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -262,27 +262,8 @@ int cpu_exec(CPUState *env1) env = env1; env_to_regs(); -#if defined(TARGET_I386) - /* put eflags in CPU temporary format */ - CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); - DF = 1 - (2 * ((env->eflags >> 10) & 1)); - CC_OP = CC_OP_EFLAGS; - env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); -#elif defined(TARGET_SPARC) -#elif defined(TARGET_M68K) - env->cc_op = CC_OP_FLAGS; - env->cc_dest = env->sr & 0xf; - env->cc_x = (env->sr >> 4) & 1; -#elif defined(TARGET_ALPHA) -#elif defined(TARGET_ARM) -#elif defined(TARGET_PPC) -#elif defined(TARGET_MIPS) -#elif defined(TARGET_SH4) -#elif defined(TARGET_CRIS) + cpu_load_flags(env); /* XXXXX */ -#else -#error unsupported target CPU -#endif env->exception_index = -1; /* prepare setjmp context for exception handling */ @@ -631,27 +612,7 @@ int cpu_exec(CPUState *env1) } } /* for(;;) */ - -#if defined(TARGET_I386) - /* restore flags in standard format */ - env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); -#elif defined(TARGET_ARM) - /* XXX: Save/restore host fpu exception state?. */ -#elif defined(TARGET_SPARC) -#elif defined(TARGET_PPC) -#elif defined(TARGET_M68K) - cpu_m68k_flush_flags(env, env->cc_op); - env->cc_op = CC_OP_FLAGS; - env->sr = (env->sr & 0xffe0) - | env->cc_dest | (env->cc_x << 4); -#elif defined(TARGET_MIPS) -#elif defined(TARGET_SH4) -#elif defined(TARGET_ALPHA) -#elif defined(TARGET_CRIS) - /* XXXXX */ -#else -#error unsupported target CPU -#endif + cpu_save_flags(env); /* restore global registers */ #include "hostregs_helper.h" diff --git a/exec-all.h b/exec-all.h index 51b27b5..0eea2f1 100644 --- a/exec-all.h +++ b/exec-all.h @@ -82,6 +82,16 @@ int cpu_restore_state_copy(struct TranslationBlock *tb, void *puc); void cpu_resume_from_signal(CPUState *env1, void *puc); void cpu_exec_init(CPUState *env); + +/* load flags for current execution. Architecture can override */ +#ifndef cpu_load_flags +#define cpu_load_flags(env) do {} while (0) +#endif +/* save flags after cpu execution. Architecture can override */ +#ifndef cpu_save_flags +#define cpu_save_flags(env) do {} while (0) +#endif + int page_unprotect(target_ulong address, unsigned long pc, void *puc); void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end, int is_cpu_write_access); diff --git a/target-i386/exec.h b/target-i386/exec.h index 5e46c5a..38ee96b 100644 --- a/target-i386/exec.h +++ b/target-i386/exec.h @@ -31,6 +31,21 @@ register struct CPUX86State *env asm(AREG0); +#define cpu_load_flags(env) \ +do { \ + /* put eflags in CPU temporary format */ \ + CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); \ + DF = 1 - (2 * ((env->eflags >> 10) & 1)); \ + CC_OP = CC_OP_EFLAGS; \ + env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);\ +} while (0) + +#define cpu_save_flags(env) \ +do { \ + /* restore flags in standard format */ \ + env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); \ +} while (0) + extern FILE *logfile; extern int loglevel; diff --git a/target-m68k/exec.h b/target-m68k/exec.h index 1269445..d4f51b3 100644 --- a/target-m68k/exec.h +++ b/target-m68k/exec.h @@ -26,6 +26,22 @@ register uint32_t T0 asm(AREG1); /* ??? We don't use T1, but common code expects it to exist */ #define T1 env->t1 +#define cpu_load_flags(env) \ +do { \ + env->cc_op = CC_OP_FLAGS; \ + env->cc_dest = env->sr & 0xf; \ + env->cc_x = (env->sr >> 4) & 1; \ +} while (0) + +#define cpu_save_flags(env) \ +do { \ + cpu_m68k_flush_flags(env, env->cc_op); \ + env->cc_op = CC_OP_FLAGS; \ + env->sr = (env->sr & 0xffe0) \ + | env->cc_dest | (env->cc_x << 4); \ +} while (0) + + #include "cpu.h" #include "exec-all.h" -- 1.5.4.5