* [Qemu-devel] [PATCH 0/5] simplify cpu_exec - again @ 2008-05-29 15:16 Glauber Costa 2008-05-29 15:16 ` [Qemu-devel] [PATCH 1/5] remove REGWPTR Glauber Costa 0 siblings, 1 reply; 6+ messages in thread From: Glauber Costa @ 2008-05-29 15:16 UTC (permalink / raw) To: qemu-devel; +Cc: kvm Hi, This version , which I'm expecting to be the last ;-), merge all comments received so far. Thank you all ^ permalink raw reply [flat|nested] 6+ messages in thread
* [Qemu-devel] [PATCH 1/5] remove REGWPTR 2008-05-29 15:16 [Qemu-devel] [PATCH 0/5] simplify cpu_exec - again Glauber Costa @ 2008-05-29 15:16 ` Glauber Costa 2008-05-29 15:16 ` [Qemu-devel] [PATCH 2/5] simplify cpu_exec Glauber Costa 0 siblings, 1 reply; 6+ messages in thread From: Glauber Costa @ 2008-05-29 15:16 UTC (permalink / raw) To: qemu-devel; +Cc: kvm Blue Swirl points out that it is not used anymore. Signed-off-by: Glauber Costa <gcosta@redhat.com> --- cpu-exec.c | 13 ------------- target-sparc/exec.h | 4 ---- 2 files changed, 0 insertions(+), 17 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index b660954..ea0e5b1 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -246,11 +246,6 @@ int cpu_exec(CPUState *env1) { #define DECLARE_HOST_REGS 1 #include "hostregs_helper.h" -#if defined(TARGET_SPARC) -#if defined(reg_REGWPTR) - uint32_t *saved_regwptr; -#endif -#endif int ret, interrupt_request; TranslationBlock *tb; uint8_t *tc_ptr; @@ -273,9 +268,6 @@ int cpu_exec(CPUState *env1) CC_OP = CC_OP_EFLAGS; env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); #elif defined(TARGET_SPARC) -#if defined(reg_REGWPTR) - saved_regwptr = REGWPTR; -#endif #elif defined(TARGET_M68K) env->cc_op = CC_OP_FLAGS; env->cc_dest = env->sr & 0xf; @@ -562,8 +554,6 @@ int cpu_exec(CPUState *env1) #elif defined(TARGET_ARM) cpu_dump_state(env, logfile, fprintf, 0); #elif defined(TARGET_SPARC) - REGWPTR = env->regbase + (env->cwp * 16); - env->regwptr = REGWPTR; cpu_dump_state(env, logfile, fprintf, 0); #elif defined(TARGET_PPC) cpu_dump_state(env, logfile, fprintf, 0); @@ -640,9 +630,6 @@ int cpu_exec(CPUState *env1) #elif defined(TARGET_ARM) /* XXX: Save/restore host fpu exception state?. */ #elif defined(TARGET_SPARC) -#if defined(reg_REGWPTR) - REGWPTR = saved_regwptr; -#endif #elif defined(TARGET_PPC) #elif defined(TARGET_M68K) cpu_m68k_flush_flags(env, env->cc_op); diff --git a/target-sparc/exec.h b/target-sparc/exec.h index 3ef0cf9..3ca0afb 100644 --- a/target-sparc/exec.h +++ b/target-sparc/exec.h @@ -18,10 +18,6 @@ register struct CPUSPARCState *env asm(AREG0); static inline void env_to_regs(void) { -#if defined(reg_REGWPTR) - REGWPTR = env->regbase + (env->cwp * 16); - env->regwptr = REGWPTR; -#endif } static inline void regs_to_env(void) -- 1.5.4.5 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Qemu-devel] [PATCH 2/5] simplify cpu_exec 2008-05-29 15:16 ` [Qemu-devel] [PATCH 1/5] remove REGWPTR Glauber Costa @ 2008-05-29 15:16 ` Glauber Costa 2008-05-29 15:16 ` [Qemu-devel] [PATCH 3/5] cpu_info_ip Glauber Costa 0 siblings, 1 reply; 6+ messages in thread From: Glauber Costa @ 2008-05-29 15:16 UTC (permalink / raw) To: qemu-devel; +Cc: kvm This is a first attempt to simplify cpu_exec(): it has simply too many ifdefs, which is not a very good practice at all. Following some work I've already posted in the past, I'm moving the target-b ifdefs to target-xxx/helper.c, encapsuled into relevant functions. Signed-off-by: Glauber Costa <gcosta@redhat.com> --- cpu-exec.c | 43 ++----------------------------------------- exec-all.h | 1 + target-alpha/exec.h | 3 +++ target-arm/exec.h | 3 +++ target-cris/exec.h | 3 +++ target-i386/exec.h | 15 +++++++++++++++ target-m68k/exec.h | 15 +++++++++++++++ target-mips/exec.h | 3 +++ target-ppc/exec.h | 3 +++ target-sh4/exec.h | 3 +++ target-sparc/exec.h | 3 +++ 11 files changed, 54 insertions(+), 41 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index ea0e5b1..4d87742 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -261,27 +261,8 @@ int cpu_exec(CPUState *env1) env = env1; env_to_regs(); -#if defined(TARGET_I386) - /* put eflags in CPU temporary format */ - CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); - DF = 1 - (2 * ((env->eflags >> 10) & 1)); - CC_OP = CC_OP_EFLAGS; - env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); -#elif defined(TARGET_SPARC) -#elif defined(TARGET_M68K) - env->cc_op = CC_OP_FLAGS; - env->cc_dest = env->sr & 0xf; - env->cc_x = (env->sr >> 4) & 1; -#elif defined(TARGET_ALPHA) -#elif defined(TARGET_ARM) -#elif defined(TARGET_PPC) -#elif defined(TARGET_MIPS) -#elif defined(TARGET_SH4) -#elif defined(TARGET_CRIS) + cpu_load_flags(env); /* XXXXX */ -#else -#error unsupported target CPU -#endif env->exception_index = -1; /* prepare setjmp context for exception handling */ @@ -623,27 +604,7 @@ int cpu_exec(CPUState *env1) } } /* for(;;) */ - -#if defined(TARGET_I386) - /* restore flags in standard format */ - env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); -#elif defined(TARGET_ARM) - /* XXX: Save/restore host fpu exception state?. */ -#elif defined(TARGET_SPARC) -#elif defined(TARGET_PPC) -#elif defined(TARGET_M68K) - cpu_m68k_flush_flags(env, env->cc_op); - env->cc_op = CC_OP_FLAGS; - env->sr = (env->sr & 0xffe0) - | env->cc_dest | (env->cc_x << 4); -#elif defined(TARGET_MIPS) -#elif defined(TARGET_SH4) -#elif defined(TARGET_ALPHA) -#elif defined(TARGET_CRIS) - /* XXXXX */ -#else -#error unsupported target CPU -#endif + cpu_save_flags(env); /* restore global registers */ #include "hostregs_helper.h" diff --git a/exec-all.h b/exec-all.h index eaf7c40..0c36c04 100644 --- a/exec-all.h +++ b/exec-all.h @@ -76,6 +76,7 @@ int cpu_restore_state_copy(struct TranslationBlock *tb, void *puc); void cpu_resume_from_signal(CPUState *env1, void *puc); void cpu_exec_init(CPUState *env); + int page_unprotect(target_ulong address, unsigned long pc, void *puc); void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end, int is_cpu_write_access); diff --git a/target-alpha/exec.h b/target-alpha/exec.h index 3b9754d..4824d0b 100644 --- a/target-alpha/exec.h +++ b/target-alpha/exec.h @@ -64,6 +64,9 @@ register uint64_t T2 asm(AREG3); #include "softmmu_exec.h" #endif /* !defined(CONFIG_USER_ONLY) */ +static inline void cpu_load_flags(CPUState *env) {} +static inline void cpu_save_flags(CPUState *env) {} + static always_inline void env_to_regs(void) { } diff --git a/target-arm/exec.h b/target-arm/exec.h index bd4910d..d52598c 100644 --- a/target-arm/exec.h +++ b/target-arm/exec.h @@ -37,6 +37,9 @@ static inline void regs_to_env(void) { } +static inline void cpu_load_flags(CPUState *env) {} +static inline void cpu_save_flags(CPUState *env) {} + int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw, int mmu_idx, int is_softmmu); diff --git a/target-cris/exec.h b/target-cris/exec.h index fe63f16..38939ac 100644 --- a/target-cris/exec.h +++ b/target-cris/exec.h @@ -44,6 +44,9 @@ static inline void regs_to_env(void) { } +static inline void cpu_load_flags(CPUState *env) {} +static inline void cpu_save_flags(CPUState *env) {} + int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw, int mmu_idx, int is_softmmu); void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr); diff --git a/target-i386/exec.h b/target-i386/exec.h index 90b82f3..c5cdbf9 100644 --- a/target-i386/exec.h +++ b/target-i386/exec.h @@ -58,6 +58,21 @@ extern int loglevel; #include "cpu.h" #include "exec-all.h" +static inline void cpu_load_flags(CPUState *env) +{ + /* put eflags in CPU temporary format */ + CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); + DF = 1 - (2 * ((env->eflags >> 10) & 1)); + CC_OP = CC_OP_EFLAGS; + env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); +} + +static inline void cpu_save_flags(CPUState *env) +{ + /* restore flags in standard format */ + env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); +} + void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); diff --git a/target-m68k/exec.h b/target-m68k/exec.h index 1269445..a19f18d 100644 --- a/target-m68k/exec.h +++ b/target-m68k/exec.h @@ -37,6 +37,21 @@ static inline void regs_to_env(void) { } +static inline void cpu_load_flags(CPUState *env) +{ + env->cc_op = CC_OP_FLAGS; + env->cc_dest = env->sr & 0xf; + env->cc_x = (env->sr >> 4) & 1; +} + +static inline void cpu_save_flags(CPUState *env) +{ + cpu_m68k_flush_flags(env, env->cc_op); + env->cc_op = CC_OP_FLAGS; + env->sr = (env->sr & 0xffe0) + | env->cc_dest | (env->cc_x << 4); +} + int cpu_m68k_handle_mmu_fault (CPUState *env, target_ulong address, int rw, int mmu_idx, int is_softmmu); diff --git a/target-mips/exec.h b/target-mips/exec.h index f10a35d..07b520b 100644 --- a/target-mips/exec.h +++ b/target-mips/exec.h @@ -44,6 +44,9 @@ register target_ulong T1 asm(AREG2); #include "cpu.h" #include "exec-all.h" +static inline void cpu_load_flags(CPUState *env) {} +static inline void cpu_save_flags(CPUState *env) {} + #if !defined(CONFIG_USER_ONLY) #include "softmmu_exec.h" #endif /* !defined(CONFIG_USER_ONLY) */ diff --git a/target-ppc/exec.h b/target-ppc/exec.h index 76fdb0b..67f33f4 100644 --- a/target-ppc/exec.h +++ b/target-ppc/exec.h @@ -27,6 +27,9 @@ #include "cpu.h" #include "exec-all.h" +static inline void cpu_load_flags(CPUState *env) {} +static inline void cpu_save_flags(CPUState *env) {} + /* For normal operations, precise emulation should not be needed */ //#define USE_PRECISE_EMULATION 1 #define USE_PRECISE_EMULATION 0 diff --git a/target-sh4/exec.h b/target-sh4/exec.h index 2d33376..ae672ac 100644 --- a/target-sh4/exec.h +++ b/target-sh4/exec.h @@ -36,6 +36,9 @@ register uint32_t T1 asm(AREG2); #include "cpu.h" #include "exec-all.h" +static inline void cpu_load_flags(CPUState *env) {} +static inline void cpu_save_flags(CPUState *env) {} + static inline int cpu_halted(CPUState *env) { if (!env->halted) return 0; diff --git a/target-sparc/exec.h b/target-sparc/exec.h index 3ca0afb..b53e9e3 100644 --- a/target-sparc/exec.h +++ b/target-sparc/exec.h @@ -24,6 +24,9 @@ static inline void regs_to_env(void) { } +static inline void cpu_load_flags(CPUState *env) {} +static inline void cpu_save_flags(CPUState *env) {} + int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw, int mmu_idx, int is_softmmu); void do_interrupt(CPUState *env); -- 1.5.4.5 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Qemu-devel] [PATCH 3/5] cpu_info_ip 2008-05-29 15:16 ` [Qemu-devel] [PATCH 2/5] simplify cpu_exec Glauber Costa @ 2008-05-29 15:16 ` Glauber Costa 2008-05-29 15:16 ` [Qemu-devel] [PATCH 4/5] simply cpu_exec further Glauber Costa 0 siblings, 1 reply; 6+ messages in thread From: Glauber Costa @ 2008-05-29 15:16 UTC (permalink / raw) To: qemu-devel; +Cc: kvm This commit makes the code for info_cpus simpler in monitor.c Signed-off-by: Glauber Costa <gcosta@redhat.com> --- exec-all.h | 2 ++ monitor.c | 17 +++++------------ target-alpha/helper.c | 2 ++ target-arm/helper.c | 2 ++ target-cris/helper.c | 2 ++ target-i386/helper.c | 6 ++++++ target-m68k/helper.c | 2 ++ target-mips/helper.c | 2 ++ target-ppc/helper.c | 6 ++++++ target-sh4/helper.c | 2 ++ target-sparc/helper.c | 6 ++++++ 11 files changed, 37 insertions(+), 12 deletions(-) diff --git a/exec-all.h b/exec-all.h index 0c36c04..072172c 100644 --- a/exec-all.h +++ b/exec-all.h @@ -77,6 +77,8 @@ int cpu_restore_state_copy(struct TranslationBlock *tb, void cpu_resume_from_signal(CPUState *env1, void *puc); void cpu_exec_init(CPUState *env); +extern int cpu_info_ip(CPUState *env, char *buf); + int page_unprotect(target_ulong address, unsigned long pc, void *puc); void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end, int is_cpu_write_access); diff --git a/monitor.c b/monitor.c index 5a9a7fa..406f6d2 100644 --- a/monitor.c +++ b/monitor.c @@ -36,6 +36,8 @@ #include "disas.h" #include <dirent.h> +#include "exec-all.h" + #ifdef CONFIG_PROFILER #include "qemu-timer.h" /* for ticks_per_sec */ #endif @@ -304,6 +306,7 @@ static void do_info_registers(void) static void do_info_cpus(void) { CPUState *env; + char buf[1024]; /* just to set the default cpu if not already done */ mon_get_cpu(); @@ -312,18 +315,8 @@ static void do_info_cpus(void) term_printf("%c CPU #%d:", (env == mon_cpu) ? '*' : ' ', env->cpu_index); -#if defined(TARGET_I386) - term_printf(" pc=0x" TARGET_FMT_lx, env->eip + env->segs[R_CS].base); -#elif defined(TARGET_PPC) - term_printf(" nip=0x" TARGET_FMT_lx, env->nip); -#elif defined(TARGET_SPARC) - term_printf(" pc=0x" TARGET_FMT_lx " npc=0x" TARGET_FMT_lx, env->pc, env->npc); -#elif defined(TARGET_MIPS) - term_printf(" PC=0x" TARGET_FMT_lx, env->PC[env->current_tc]); -#endif - if (env->halted) - term_printf(" (halted)"); - term_printf("\n"); + if (cpu_info_ip(env, buf)) + term_printf("%s %s\n", buf, env->halted ? "(halted)" : ""); } } diff --git a/target-alpha/helper.c b/target-alpha/helper.c index fd39f5f..507929e 100644 --- a/target-alpha/helper.c +++ b/target-alpha/helper.c @@ -452,3 +452,5 @@ void cpu_dump_EA (target_ulong EA) f = stdout; fprintf(f, "Memory access at address " TARGET_FMT_lx "\n", EA); } + +int cpu_info_ip(CPUState *env, char *buf) { return 0; } diff --git a/target-arm/helper.c b/target-arm/helper.c index 8e85435..8dd6209 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2522,3 +2522,5 @@ uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env) tmp = float32_scalbn(tmp, 31, s); return float32_to_int32(tmp, s); } + +int cpu_info_ip(CPUState *env, char *buf) { return 0; } diff --git a/target-cris/helper.c b/target-cris/helper.c index c16a58a..5e566b4 100644 --- a/target-cris/helper.c +++ b/target-cris/helper.c @@ -182,3 +182,5 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) return phy; } #endif + +int cpu_info_ip(CPUState *env, char *buf) { return 0; } diff --git a/target-i386/helper.c b/target-i386/helper.c index f993fa7..997e377 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -779,6 +779,12 @@ void cpu_x86_flush_tlb(CPUX86State *env, target_ulong addr) tlb_flush_page(env, addr); } +int cpu_info_ip(CPUState *env, char *buf) +{ + sprintf(buf, " pc=0x" TARGET_FMT_lx, env->eip + env->segs[R_CS].base); + return 1; +} + #if defined(CONFIG_USER_ONLY) int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, diff --git a/target-m68k/helper.c b/target-m68k/helper.c index 7f01392..4503006 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -880,3 +880,5 @@ void HELPER(set_mac_extu)(CPUState *env, uint32_t val, uint32_t acc) res |= (uint64_t)(val & 0xffff0000) << 16; env->macc[acc + 1] = res; } + +int cpu_info_ip(CPUState *env, char *buf) { return 0; } diff --git a/target-mips/helper.c b/target-mips/helper.c index b962295..3e0b172 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -636,3 +636,5 @@ void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra) } } } + +int cpu_info_ip(CPUState *env, char *buf) { return 0; } diff --git a/target-ppc/helper.c b/target-ppc/helper.c index 2a52dc6..464a92e 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -2988,3 +2988,9 @@ void cpu_ppc_close (CPUPPCState *env) /* Should also remove all opcode tables... */ qemu_free(env); } + +int cpu_info_ip(CPUState *env, char *buf) +{ + sprintf(buf, " nip=0x" TARGET_FMT_lx, env->nip); + return 1; +} diff --git a/target-sh4/helper.c b/target-sh4/helper.c index 917f02f..1e5ca19 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -534,3 +534,5 @@ void cpu_load_tlb(CPUState * env) } #endif + +int cpu_info_ip(CPUState *env, char *buf) { return 0; } diff --git a/target-sparc/helper.c b/target-sparc/helper.c index 8bf40e4..9b6eba4 100644 --- a/target-sparc/helper.c +++ b/target-sparc/helper.c @@ -1525,6 +1525,12 @@ void cpu_dump_state(CPUState *env, FILE *f, cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env)); } +int cpu_info_ip(CPUState *env, char *buf) +{ + sprintf(buf, " pc=0x" TARGET_FMT_lx " npc=0x" TARGET_FMT_lx, env->pc, env->npc); + return 1; +} + #ifdef TARGET_SPARC64 #if !defined(CONFIG_USER_ONLY) #include "qemu-common.h" -- 1.5.4.5 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Qemu-devel] [PATCH 4/5] simply cpu_exec further 2008-05-29 15:16 ` [Qemu-devel] [PATCH 3/5] cpu_info_ip Glauber Costa @ 2008-05-29 15:16 ` Glauber Costa 2008-05-29 15:16 ` [Qemu-devel] [PATCH 5/5] cpu-exec-dump Glauber Costa 0 siblings, 1 reply; 6+ messages in thread From: Glauber Costa @ 2008-05-29 15:16 UTC (permalink / raw) To: qemu-devel; +Cc: kvm We change interrupt functions so they have the same signature, getting only an env parameter. When necessary, some more attributed were added to the relevant CPUState to make it possible. Signed-off-by: Glauber Costa <gcosta@redhat.com> --- cpu-defs.h | 1 + cpu-exec.c | 198 +++++------------------------------------------ exec-all.h | 7 ++ target-alpha/helper.c | 9 ++ target-arm/helper.c | 27 +++++++ target-cris/helper.c | 9 ++ target-i386/exec.h | 5 +- target-i386/op_helper.c | 68 ++++++++++++++++- target-m68k/cpu.h | 2 +- target-m68k/helper.c | 16 ++++ target-m68k/op_helper.c | 8 +- target-mips/helper.c | 16 ++++ target-ppc/helper.c | 15 ++++ target-sh4/helper.c | 8 ++ target-sparc/helper.c | 24 ++++++ 15 files changed, 224 insertions(+), 189 deletions(-) diff --git a/cpu-defs.h b/cpu-defs.h index f7f5f17..33d47e8 100644 --- a/cpu-defs.h +++ b/cpu-defs.h @@ -163,6 +163,7 @@ typedef struct CPUTLBEntry { /* Core interrupt code */ \ jmp_buf jmp_env; \ int exception_index; \ + int exception_is_hw; \ \ void *next_cpu; /* next CPU sharing TB cache */ \ int cpu_index; /* CPU index (informative) */ \ diff --git a/cpu-exec.c b/cpu-exec.c index 4d87742..9526608 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -240,6 +240,21 @@ static inline TranslationBlock *tb_find_fast(void) return tb; } +void handle_interrupt_common(CPUState *env) +{ + if (env->interrupt_request & CPU_INTERRUPT_HALT) { + env->interrupt_request &= ~CPU_INTERRUPT_HALT; + env->halted = 1; + env->exception_index = EXCP_HLT; + cpu_loop_exit(); + } +} + +void reset_tb(void) +{ + next_tb = 0; +} + /* main execution loop */ int cpu_exec(CPUState *env1) @@ -280,43 +295,16 @@ int cpu_exec(CPUState *env1) which will be handled outside the cpu execution loop */ #if defined(TARGET_I386) - do_interrupt_user(env->exception_index, - env->exception_is_int, - env->error_code, - env->exception_next_eip); - /* successfully delivered */ - env->old_exception = -1; + do_interrupt(env); #endif ret = env->exception_index; break; } else { -#if defined(TARGET_I386) /* simulate a real cpu exception. On i386, it can trigger new exceptions, but we do not handle double or triple faults yet. */ - do_interrupt(env->exception_index, - env->exception_is_int, - env->error_code, - env->exception_next_eip, 0); - /* successfully delivered */ - env->old_exception = -1; -#elif defined(TARGET_PPC) - do_interrupt(env); -#elif defined(TARGET_MIPS) - do_interrupt(env); -#elif defined(TARGET_SPARC) - do_interrupt(env); -#elif defined(TARGET_ARM) - do_interrupt(env); -#elif defined(TARGET_SH4) - do_interrupt(env); -#elif defined(TARGET_ALPHA) + env->exception_is_hw = 0; do_interrupt(env); -#elif defined(TARGET_CRIS) - do_interrupt(env); -#elif defined(TARGET_M68K) - do_interrupt(0); -#endif } env->exception_index = -1; } @@ -359,157 +347,9 @@ int cpu_exec(CPUState *env1) env->exception_index = EXCP_DEBUG; cpu_loop_exit(); } -#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \ - defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) - if (interrupt_request & CPU_INTERRUPT_HALT) { - env->interrupt_request &= ~CPU_INTERRUPT_HALT; - env->halted = 1; - env->exception_index = EXCP_HLT; - cpu_loop_exit(); - } -#endif -#if defined(TARGET_I386) - if ((interrupt_request & CPU_INTERRUPT_SMI) && - !(env->hflags & HF_SMM_MASK)) { - svm_check_intercept(SVM_EXIT_SMI); - env->interrupt_request &= ~CPU_INTERRUPT_SMI; - do_smm_enter(); - next_tb = 0; - } else if ((interrupt_request & CPU_INTERRUPT_NMI) && - !(env->hflags & HF_NMI_MASK)) { - env->interrupt_request &= ~CPU_INTERRUPT_NMI; - env->hflags |= HF_NMI_MASK; - do_interrupt(EXCP02_NMI, 0, 0, 0, 1); - next_tb = 0; - } else if ((interrupt_request & CPU_INTERRUPT_HARD) && - (env->eflags & IF_MASK || env->hflags & HF_HIF_MASK) && - !(env->hflags & HF_INHIBIT_IRQ_MASK)) { - int intno; - svm_check_intercept(SVM_EXIT_INTR); - env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ); - intno = cpu_get_pic_interrupt(env); - if (loglevel & CPU_LOG_TB_IN_ASM) { - fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno); - } - do_interrupt(intno, 0, 0, 0, 1); - /* ensure that no TB jump will be modified as - the program flow was changed */ - next_tb = 0; -#if !defined(CONFIG_USER_ONLY) - } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) && - (env->eflags & IF_MASK) && !(env->hflags & HF_INHIBIT_IRQ_MASK)) { - int intno; - /* FIXME: this should respect TPR */ - env->interrupt_request &= ~CPU_INTERRUPT_VIRQ; - svm_check_intercept(SVM_EXIT_VINTR); - intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector)); - if (loglevel & CPU_LOG_TB_IN_ASM) - fprintf(logfile, "Servicing virtual hardware INT=0x%02x\n", intno); - do_interrupt(intno, 0, 0, -1, 1); - stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl), - ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl)) & ~V_IRQ_MASK); - next_tb = 0; -#endif - } -#elif defined(TARGET_PPC) -#if 0 - if ((interrupt_request & CPU_INTERRUPT_RESET)) { - cpu_ppc_reset(env); - } -#endif - if (interrupt_request & CPU_INTERRUPT_HARD) { - ppc_hw_interrupt(env); - if (env->pending_interrupts == 0) - env->interrupt_request &= ~CPU_INTERRUPT_HARD; - next_tb = 0; - } -#elif defined(TARGET_MIPS) - if ((interrupt_request & CPU_INTERRUPT_HARD) && - (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) && - (env->CP0_Status & (1 << CP0St_IE)) && - !(env->CP0_Status & (1 << CP0St_EXL)) && - !(env->CP0_Status & (1 << CP0St_ERL)) && - !(env->hflags & MIPS_HFLAG_DM)) { - /* Raise it */ - env->exception_index = EXCP_EXT_INTERRUPT; - env->error_code = 0; - do_interrupt(env); - next_tb = 0; - } -#elif defined(TARGET_SPARC) - if ((interrupt_request & CPU_INTERRUPT_HARD) && - (env->psret != 0)) { - int pil = env->interrupt_index & 15; - int type = env->interrupt_index & 0xf0; - - if (((type == TT_EXTINT) && - (pil == 15 || pil > env->psrpil)) || - type != TT_EXTINT) { - env->interrupt_request &= ~CPU_INTERRUPT_HARD; - env->exception_index = env->interrupt_index; - do_interrupt(env); - env->interrupt_index = 0; -#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) - cpu_check_irqs(env); -#endif - next_tb = 0; - } - } else if (interrupt_request & CPU_INTERRUPT_TIMER) { - //do_interrupt(0, 0, 0, 0, 0); - env->interrupt_request &= ~CPU_INTERRUPT_TIMER; - } -#elif defined(TARGET_ARM) - if (interrupt_request & CPU_INTERRUPT_FIQ - && !(env->uncached_cpsr & CPSR_F)) { - env->exception_index = EXCP_FIQ; - do_interrupt(env); - next_tb = 0; - } - /* ARMv7-M interrupt return works by loading a magic value - into the PC. On real hardware the load causes the - return to occur. The qemu implementation performs the - jump normally, then does the exception return when the - CPU tries to execute code at the magic address. - This will cause the magic PC value to be pushed to - the stack if an interrupt occured at the wrong time. - We avoid this by disabling interrupts when - pc contains a magic address. */ - if (interrupt_request & CPU_INTERRUPT_HARD - && ((IS_M(env) && env->regs[15] < 0xfffffff0) - || !(env->uncached_cpsr & CPSR_I))) { - env->exception_index = EXCP_IRQ; - do_interrupt(env); - next_tb = 0; - } -#elif defined(TARGET_SH4) - if (interrupt_request & CPU_INTERRUPT_HARD) { - do_interrupt(env); - next_tb = 0; - } -#elif defined(TARGET_ALPHA) - if (interrupt_request & CPU_INTERRUPT_HARD) { - do_interrupt(env); - next_tb = 0; - } -#elif defined(TARGET_CRIS) - if (interrupt_request & CPU_INTERRUPT_HARD) { - do_interrupt(env); - next_tb = 0; - } -#elif defined(TARGET_M68K) - if (interrupt_request & CPU_INTERRUPT_HARD - && ((env->sr & SR_I) >> SR_I_SHIFT) - < env->pending_level) { - /* Real hardware gets the interrupt vector via an - IACK cycle at this point. Current emulated - hardware doesn't rely on this, so we - provide/save the vector when the interrupt is - first signalled. */ - env->exception_index = env->pending_vector; - do_interrupt(1); - next_tb = 0; - } -#endif + + cpu_handle_interrupt_request(env); + /* Don't use the cached interupt_request value, do_interrupt may have updated the EXITTB flag. */ if (env->interrupt_request & CPU_INTERRUPT_EXITTB) { diff --git a/exec-all.h b/exec-all.h index 072172c..3a6f2a5 100644 --- a/exec-all.h +++ b/exec-all.h @@ -79,6 +79,13 @@ void cpu_exec_init(CPUState *env); extern int cpu_info_ip(CPUState *env, char *buf); +/* implemented by the targets */ +void cpu_handle_interrupt_request(CPUState *env); +void do_interrupt(CPUState *env); +/* implemented by cpu-exec.c */ +void handle_interrupt_common(CPUState *env); +void reset_tb(void); + int page_unprotect(target_ulong address, unsigned long pc, void *puc); void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end, int is_cpu_write_access); diff --git a/target-alpha/helper.c b/target-alpha/helper.c index 507929e..593f600 100644 --- a/target-alpha/helper.c +++ b/target-alpha/helper.c @@ -454,3 +454,12 @@ void cpu_dump_EA (target_ulong EA) } int cpu_info_ip(CPUState *env, char *buf) { return 0; } + +void cpu_handle_interrupt_request(CPUState *env) +{ + handle_interrupt_common(env); + if (env->interrupt_request & CPU_INTERRUPT_HARD) { + do_interrupt(env); + reset_tb(); + } +} diff --git a/target-arm/helper.c b/target-arm/helper.c index 8dd6209..80eda6f 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2524,3 +2524,30 @@ uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env) } int cpu_info_ip(CPUState *env, char *buf) { return 0; } + +void cpu_handle_interrupt_request(CPUState *env) +{ + handle_interrupt_common(env); + if (env->interrupt_request & CPU_INTERRUPT_FIQ + && !(env->uncached_cpsr & CPSR_F)) { + env->exception_index = EXCP_FIQ; + do_interrupt(env); + reset_tb(); + } + /* ARMv7-M interrupt return works by loading a magic value + into the PC. On real hardware the load causes the + return to occur. The qemu implementation performs the + jump normally, then does the exception return when the + CPU tries to execute code at the magic address. + This will cause the magic PC value to be pushed to + the stack if an interrupt occured at the wrong time. + We avoid this by disabling interrupts when + pc contains a magic address. */ + if (env->interrupt_request & CPU_INTERRUPT_HARD + && ((IS_M(env) && env->regs[15] < 0xfffffff0) + || !(env->uncached_cpsr & CPSR_I))) { + env->exception_index = EXCP_IRQ; + do_interrupt(env); + reset_tb(); + } +} diff --git a/target-cris/helper.c b/target-cris/helper.c index 5e566b4..5ae7c52 100644 --- a/target-cris/helper.c +++ b/target-cris/helper.c @@ -184,3 +184,12 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) #endif int cpu_info_ip(CPUState *env, char *buf) { return 0; } + +void cpu_handle_interrupt_request(CPUState *env) +{ + handle_interrupt_common(env); + if (env->interrupt_request & CPU_INTERRUPT_HARD) { + do_interrupt(env); + reset_tb(); + } +} diff --git a/target-i386/exec.h b/target-i386/exec.h index c5cdbf9..1a7f563 100644 --- a/target-i386/exec.h +++ b/target-i386/exec.h @@ -83,10 +83,7 @@ void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr); void __hidden cpu_lock(void); void __hidden cpu_unlock(void); -void do_interrupt(int intno, int is_int, int error_code, - target_ulong next_eip, int is_hw); -void do_interrupt_user(int intno, int is_int, int error_code, - target_ulong next_eip); +void do_interrupt(CPUState *env); void raise_interrupt(int intno, int is_int, int error_code, int next_eip_addend); void raise_exception_err(int exception_index, int error_code); diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c index bb76618..3e7fb01 100644 --- a/target-i386/op_helper.c +++ b/target-i386/op_helper.c @@ -1182,7 +1182,7 @@ void do_interrupt_user(int intno, int is_int, int error_code, * the int instruction. next_eip is the EIP value AFTER the interrupt * instruction. It is only relevant if is_int is TRUE. */ -void do_interrupt(int intno, int is_int, int error_code, +void do_interrupt_system(int intno, int is_int, int error_code, target_ulong next_eip, int is_hw) { if (loglevel & CPU_LOG_INT) { @@ -1230,6 +1230,72 @@ void do_interrupt(int intno, int is_int, int error_code, } } +void do_interrupt(CPUState *env) +{ + if (env->user_mode_only) + do_interrupt_user(env->exception_index, + env->exception_is_int, + env->error_code, + env->exception_next_eip); + else + do_interrupt_system(env->exception_index, + env->exception_is_int, + env->error_code, + env->exception_next_eip, + env->exception_is_hw); + + env->old_exception = -1; +} + +void cpu_handle_interrupt_request(CPUState *env) +{ + int interrupt_request = env->interrupt_request; + int intno; + + if ((interrupt_request & CPU_INTERRUPT_SMI) && + !(env->hflags & HF_SMM_MASK)) { + svm_check_intercept(SVM_EXIT_SMI); + env->interrupt_request &= ~CPU_INTERRUPT_SMI; + do_smm_enter(); + reset_tb(); + } else if ((interrupt_request & CPU_INTERRUPT_NMI) && + !(env->hflags & HF_NMI_MASK)) { + env->interrupt_request &= ~CPU_INTERRUPT_NMI; + env->hflags |= HF_NMI_MASK; + do_interrupt_system(EXCP02_NMI, 0, 0, 0, 1); + reset_tb(); + } else if ((interrupt_request & CPU_INTERRUPT_HARD) && + (env->eflags & IF_MASK || env->hflags & HF_HIF_MASK) && + !(env->hflags & HF_INHIBIT_IRQ_MASK)) { + svm_check_intercept(SVM_EXIT_INTR); + env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ); + intno = cpu_get_pic_interrupt(env); + if (loglevel & CPU_LOG_TB_IN_ASM) { + fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno); + } + + do_interrupt_system(intno, 0, 0, 0, 1); + /* ensure that no TB jump will be modified as + the program flow was changed */ + reset_tb(); +#if !defined(CONFIG_USER_ONLY) + } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) && + (env->eflags & IF_MASK) && !(env->hflags & HF_INHIBIT_IRQ_MASK)) { + /* FIXME: this should respect TPR */ + env->interrupt_request &= ~CPU_INTERRUPT_VIRQ; + svm_check_intercept(SVM_EXIT_VINTR); + intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector)); + if (loglevel & CPU_LOG_TB_IN_ASM) + fprintf(logfile, "Servicing virtual hardware INT=0x%02x\n", intno); + + do_interrupt_system(intno, 0, 0, -1, 1); + stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl), + ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl)) & ~V_IRQ_MASK); + reset_tb(); +#endif + } +} + /* * Check nested exceptions and change to double or triple fault if * needed. It should only be called, if this is not an interrupt. diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h index d5c5a10..027ae61 100644 --- a/target-m68k/cpu.h +++ b/target-m68k/cpu.h @@ -121,7 +121,7 @@ void m68k_tcg_init(void); CPUM68KState *cpu_m68k_init(const char *cpu_model); int cpu_m68k_exec(CPUM68KState *s); void cpu_m68k_close(CPUM68KState *s); -void do_interrupt(int is_hw); +void do_interrupt(CPUM68KState *s); /* you can call this signal handler from your SIGBUS and SIGSEGV signal handlers to inform the virtual CPU of exceptions. non zero is returned if the signal was handled by the virtual CPU. */ diff --git a/target-m68k/helper.c b/target-m68k/helper.c index 4503006..83f0fe0 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -305,6 +305,22 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) return addr; } +void cpu_handle_interrupt_request(CPUState *env) +{ + if (env->interrupt_request & CPU_INTERRUPT_HARD + && ((env->sr & SR_I) >> SR_I_SHIFT) + < env->pending_level) { + /* Real hardware gets the interrupt vector via an + IACK cycle at this point. Current emulated + hardware doesn't rely on this, so we + provide/save the vector when the interrupt is + signalled. */ + env->exception_index = env->pending_vector; + env->exception_is_hw = 1; + do_interrupt(env); + reset_tb(); + } +} #if defined(CONFIG_USER_ONLY) int cpu_m68k_handle_mmu_fault (CPUState *env, target_ulong address, int rw, diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c index f2e9f03..0233911 100644 --- a/target-m68k/op_helper.c +++ b/target-m68k/op_helper.c @@ -22,7 +22,7 @@ #if defined(CONFIG_USER_ONLY) -void do_interrupt(int is_hw) +void do_interrupt(CPUState *env) { env->exception_index = -1; } @@ -91,7 +91,7 @@ static void do_rte(void) env->aregs[7] = sp + 8; } -void do_interrupt(int is_hw) +void do_interrupt(CPUState *env) { uint32_t sp; uint32_t fmt; @@ -101,7 +101,7 @@ void do_interrupt(int is_hw) fmt = 0; retaddr = env->pc; - if (!is_hw) { + if (!env->exception_is_hw) { switch (env->exception_index) { case EXCP_RTE: /* Return from an exception. */ @@ -139,7 +139,7 @@ void do_interrupt(int is_hw) fmt |= env->sr; env->sr |= SR_S; - if (is_hw) { + if (env->exception_is_hw) { env->sr = (env->sr & ~SR_I) | (env->pending_level << SR_I_SHIFT); env->sr &= ~SR_M; } diff --git a/target-mips/helper.c b/target-mips/helper.c index 3e0b172..2cd322a 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -583,6 +583,22 @@ void do_interrupt (CPUState *env) env->exception_index = EXCP_NONE; } +void cpu_handle_interrupt_request(CPUState *env) +{ + handle_interrupt_common(env); + if ((env->interrupt_request & CPU_INTERRUPT_HARD) && + (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) && + (env->CP0_Status & (1 << CP0St_IE)) && + !(env->CP0_Status & (1 << CP0St_EXL)) && + !(env->CP0_Status & (1 << CP0St_ERL)) && + !(env->hflags & MIPS_HFLAG_DM)) { + /* Raise it */ + env->exception_index = EXCP_EXT_INTERRUPT; + env->error_code = 0; + do_interrupt(env); + reset_tb(); + } +} void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra) { r4k_tlb_t *tlb; diff --git a/target-ppc/helper.c b/target-ppc/helper.c index 464a92e..d6a3ea5 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -2994,3 +2994,18 @@ int cpu_info_ip(CPUState *env, char *buf) sprintf(buf, " nip=0x" TARGET_FMT_lx, env->nip); return 1; } + +void cpu_handle_interrupt_request(CPUState *env) +{ +#if 0 + if ((interrupt_request & CPU_INTERRUPT_RESET)) { + cpu_ppc_reset(env); + } +#endif + if (env->interrupt_request & CPU_INTERRUPT_HARD) { + ppc_hw_interrupt(env); + if (env->pending_interrupts == 0) + env->interrupt_request &= ~CPU_INTERRUPT_HARD; + reset_tb(); + } +} diff --git a/target-sh4/helper.c b/target-sh4/helper.c index 1e5ca19..7043fb4 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -536,3 +536,11 @@ void cpu_load_tlb(CPUState * env) #endif int cpu_info_ip(CPUState *env, char *buf) { return 0; } + +void cpu_handle_interrupt_request(CPUState *env) +{ + if (env->interrupt_request & CPU_INTERRUPT_HARD) { + do_interrupt(env); + reset_tb(); + } +} diff --git a/target-sparc/helper.c b/target-sparc/helper.c index 9b6eba4..39f077a 100644 --- a/target-sparc/helper.c +++ b/target-sparc/helper.c @@ -866,6 +866,30 @@ void do_interrupt(CPUState *env) } #endif +void cpu_handle_interrupt_request(CPUState *env) +{ + handle_interrupt_common(env); + if ((env->interrupt_request & CPU_INTERRUPT_HARD) && (env->psret != 0)) { + int pil = env->interrupt_index & 15; + int type = env->interrupt_index & 0xf0; + + if (((type == TT_EXTINT) && + (pil == 15 || pil > env->psrpil)) || type != TT_EXTINT) { + env->interrupt_request &= ~CPU_INTERRUPT_HARD; + env->exception_index = env->interrupt_index; + do_interrupt(env); + env->interrupt_index = 0; +#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) + cpu_check_irqs(env); +#endif + reset_tb(); + } + } else if (env->interrupt_request & CPU_INTERRUPT_TIMER) { + //do_interrupt(0, 0, 0, 0, 0); + env->interrupt_request &= ~CPU_INTERRUPT_TIMER; + } +} + void memcpy32(target_ulong *dst, const target_ulong *src) { dst[0] = src[0]; -- 1.5.4.5 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Qemu-devel] [PATCH 5/5] cpu-exec-dump 2008-05-29 15:16 ` [Qemu-devel] [PATCH 4/5] simply cpu_exec further Glauber Costa @ 2008-05-29 15:16 ` Glauber Costa 0 siblings, 0 replies; 6+ messages in thread From: Glauber Costa @ 2008-05-29 15:16 UTC (permalink / raw) To: qemu-devel; +Cc: kvm enclose the cpu dumping logic in cpu_exec() inside cpu_exec_dump() --- cpu-exec.c | 29 ++--------------------------- exec-all.h | 2 ++ target-alpha/helper.c | 5 +++++ target-arm/helper.c | 5 +++++ target-cris/helper.c | 5 +++++ target-i386/exec.h | 2 ++ target-i386/helper.c | 6 ++++++ target-m68k/helper.c | 5 +++++ target-mips/helper.c | 5 +++++ target-ppc/helper.c | 5 +++++ target-sh4/helper.c | 5 +++++ target-sparc/helper.c | 5 +++++ 12 files changed, 52 insertions(+), 27 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index 9526608..df652fd 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -368,33 +368,8 @@ int cpu_exec(CPUState *env1) if ((loglevel & CPU_LOG_TB_CPU)) { /* restore flags in standard format */ regs_to_env(); -#if defined(TARGET_I386) - env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); - cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); - env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); -#elif defined(TARGET_ARM) - cpu_dump_state(env, logfile, fprintf, 0); -#elif defined(TARGET_SPARC) - cpu_dump_state(env, logfile, fprintf, 0); -#elif defined(TARGET_PPC) - cpu_dump_state(env, logfile, fprintf, 0); -#elif defined(TARGET_M68K) - cpu_m68k_flush_flags(env, env->cc_op); - env->cc_op = CC_OP_FLAGS; - env->sr = (env->sr & 0xffe0) - | env->cc_dest | (env->cc_x << 4); - cpu_dump_state(env, logfile, fprintf, 0); -#elif defined(TARGET_MIPS) - cpu_dump_state(env, logfile, fprintf, 0); -#elif defined(TARGET_SH4) - cpu_dump_state(env, logfile, fprintf, 0); -#elif defined(TARGET_ALPHA) - cpu_dump_state(env, logfile, fprintf, 0); -#elif defined(TARGET_CRIS) - cpu_dump_state(env, logfile, fprintf, 0); -#else -#error unsupported target CPU -#endif + cpu_save_flags(env); + cpu_exec_dump(env); } #endif tb = tb_find_fast(); diff --git a/exec-all.h b/exec-all.h index 3a6f2a5..139b975 100644 --- a/exec-all.h +++ b/exec-all.h @@ -79,6 +79,8 @@ void cpu_exec_init(CPUState *env); extern int cpu_info_ip(CPUState *env, char *buf); +void cpu_exec_dump(CPUState *env); + /* implemented by the targets */ void cpu_handle_interrupt_request(CPUState *env); void do_interrupt(CPUState *env); diff --git a/target-alpha/helper.c b/target-alpha/helper.c index 593f600..16843c5 100644 --- a/target-alpha/helper.c +++ b/target-alpha/helper.c @@ -463,3 +463,8 @@ void cpu_handle_interrupt_request(CPUState *env) reset_tb(); } } + +void cpu_exec_dump(CPUState *env) +{ + cpu_dump_state(env, logfile, fprintf, 0); +} diff --git a/target-arm/helper.c b/target-arm/helper.c index 80eda6f..61a07c7 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2551,3 +2551,8 @@ void cpu_handle_interrupt_request(CPUState *env) reset_tb(); } } + +void cpu_exec_dump(CPUState *env) +{ + cpu_dump_state(env, logfile, fprintf, 0); +} diff --git a/target-cris/helper.c b/target-cris/helper.c index 5ae7c52..67ecf84 100644 --- a/target-cris/helper.c +++ b/target-cris/helper.c @@ -193,3 +193,8 @@ void cpu_handle_interrupt_request(CPUState *env) reset_tb(); } } + +void cpu_exec_dump(CPUState *env) +{ + cpu_dump_state(env, logfile, fprintf, 0); +} diff --git a/target-i386/exec.h b/target-i386/exec.h index 1a7f563..8a5d616 100644 --- a/target-i386/exec.h +++ b/target-i386/exec.h @@ -31,6 +31,8 @@ register struct CPUX86State *env asm(AREG0); +#define cpu_exec_dump x86_cpu_exec_dump + extern FILE *logfile; extern int loglevel; diff --git a/target-i386/helper.c b/target-i386/helper.c index 997e377..a662dea 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -785,6 +785,12 @@ int cpu_info_ip(CPUState *env, char *buf) return 1; } +void cpu_exec_dump(CPUState *env) +{ + cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); + env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); +} + #if defined(CONFIG_USER_ONLY) int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, diff --git a/target-m68k/helper.c b/target-m68k/helper.c index 83f0fe0..ad1908e 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -898,3 +898,8 @@ void HELPER(set_mac_extu)(CPUState *env, uint32_t val, uint32_t acc) } int cpu_info_ip(CPUState *env, char *buf) { return 0; } + +void cpu_exec_dump(CPUState *env) +{ + cpu_dump_state(env, logfile, fprintf, 0); +} diff --git a/target-mips/helper.c b/target-mips/helper.c index 2cd322a..832d506 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -654,3 +654,8 @@ void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra) } int cpu_info_ip(CPUState *env, char *buf) { return 0; } + +void cpu_exec_dump(CPUState *env) +{ + cpu_dump_state(env, logfile, fprintf, 0); +} diff --git a/target-ppc/helper.c b/target-ppc/helper.c index d6a3ea5..c97f733 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -3009,3 +3009,8 @@ void cpu_handle_interrupt_request(CPUState *env) reset_tb(); } } + +void cpu_exec_dump(CPUState *env) +{ + cpu_dump_state(env, logfile, fprintf, 0); +} diff --git a/target-sh4/helper.c b/target-sh4/helper.c index 7043fb4..d75bf3b 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -544,3 +544,8 @@ void cpu_handle_interrupt_request(CPUState *env) reset_tb(); } } + +void cpu_exec_dump(CPUState *env) +{ + cpu_dump_state(env, logfile, fprintf, 0); +} diff --git a/target-sparc/helper.c b/target-sparc/helper.c index 39f077a..6cb67d9 100644 --- a/target-sparc/helper.c +++ b/target-sparc/helper.c @@ -1585,3 +1585,8 @@ void helper_tick_set_limit(void *opaque, uint64_t limit) #endif } #endif + +void cpu_exec_dump(CPUState *env) +{ + cpu_dump_state(env, logfile, fprintf, 0); +} -- 1.5.4.5 ^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2008-05-29 15:16 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2008-05-29 15:16 [Qemu-devel] [PATCH 0/5] simplify cpu_exec - again Glauber Costa 2008-05-29 15:16 ` [Qemu-devel] [PATCH 1/5] remove REGWPTR Glauber Costa 2008-05-29 15:16 ` [Qemu-devel] [PATCH 2/5] simplify cpu_exec Glauber Costa 2008-05-29 15:16 ` [Qemu-devel] [PATCH 3/5] cpu_info_ip Glauber Costa 2008-05-29 15:16 ` [Qemu-devel] [PATCH 4/5] simply cpu_exec further Glauber Costa 2008-05-29 15:16 ` [Qemu-devel] [PATCH 5/5] cpu-exec-dump Glauber Costa
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