[Qemu-devel] [PATCH] Fix i386 segment descriptor types on reset

[Qemu-devel] [PATCH] Fix i386 segment descriptor types on reset

[Avi Kivity]

On reset, qemu loads incorrect segment types into the segment caches.
This doesn't affect anything as qemu doesn't check segment attributes,
but may be a problem if qemu emulation accuracy improves.

It is also needed for kvm, as hardware virtualization extensions check
the segment attributes.

Signed-off-by: Avi Kivity <avi@qumranet.com>

diff --git a/target-i386/helper.c b/target-i386/helper.c
index d3bfb9a..9d88cea 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -383,16 +393,22 @@ void cpu_reset(CPUX86State *env)
     env->idt.limit = 0xffff;
     env->gdt.limit = 0xffff;
     env->ldt.limit = 0xffff;
-    env->ldt.flags = DESC_P_MASK;
+    env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
     env->tr.limit = 0xffff;
-    env->tr.flags = DESC_P_MASK;
-
-    cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 0);
-    cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 0);
-    cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 0);
-    cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 0);
-    cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 0);
-    cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 0);
+    env->tr.flags = DESC_P_MASK | (11 < DESC_TYPE_SHIFT);
+
+    cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
+                           DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | DESC_R_MASK);
+    cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
+                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
+    cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
+                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
+    cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
+                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
+    cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
+                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
+    cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
+                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
 
     env->eip = 0xfff0;
     env->regs[R_EDX] = env->cpuid_version;