From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1K4Gn7-0004W2-6G for qemu-devel@nongnu.org; Thu, 05 Jun 2008 10:50:13 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1K4Gn2-0004Sg-3K for qemu-devel@nongnu.org; Thu, 05 Jun 2008 10:50:12 -0400 Received: from [199.232.76.173] (port=57120 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1K4Gn1-0004Sd-TX for qemu-devel@nongnu.org; Thu, 05 Jun 2008 10:50:07 -0400 Received: from il.qumranet.com ([212.179.150.194]:34990) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1K4Gn1-00034O-Cs for qemu-devel@nongnu.org; Thu, 05 Jun 2008 10:50:07 -0400 From: Avi Kivity Date: Thu, 5 Jun 2008 17:50:02 +0300 Message-Id: <1212677402-10515-1-git-send-email-avi@qumranet.com> Subject: [Qemu-devel] [PATCH] Fix i386 segment descriptor types on reset Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On reset, qemu loads incorrect segment types into the segment caches. This doesn't affect anything as qemu doesn't check segment attributes, but may be a problem if qemu emulation accuracy improves. It is also needed for kvm, as hardware virtualization extensions check the segment attributes. Signed-off-by: Avi Kivity diff --git a/target-i386/helper.c b/target-i386/helper.c index d3bfb9a..9d88cea 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -383,16 +393,22 @@ void cpu_reset(CPUX86State *env) env->idt.limit = 0xffff; env->gdt.limit = 0xffff; env->ldt.limit = 0xffff; - env->ldt.flags = DESC_P_MASK; + env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); env->tr.limit = 0xffff; - env->tr.flags = DESC_P_MASK; - - cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 0); - cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 0); - cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 0); - cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 0); - cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 0); - cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 0); + env->tr.flags = DESC_P_MASK | (11 < DESC_TYPE_SHIFT); + + cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, + DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | DESC_R_MASK); + cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); + cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); + cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); + cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); + cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); env->eip = 0xfff0; env->regs[R_EDX] = env->cpuid_version;