[Qemu-devel] [PATCH] ARM CP14 trivial support

[Daniel Silverstone <dsilvers@simtec.co.uk>]

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Hi,

Continuing the patch series aiming at supporting Simtec's development
boards and other Samsung SoC based systems, attached is a patch which
provides trivial coprocessor 14 support.

Regards,

Daniel.

-- 
Daniel Silverstone                              http://www.simtec.co.uk/
PGP mail accepted and encouraged.            Key Id: 2BC8 4016 2068 7895


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ARM9 CP14 support

The ARM coprocessor number 14, in part, is responsible for describing
CPU features. It is also the interface to the JTAG DCC channel which
some systems use to control early-boot-time debugging. All this patch
does is provide enough support that reading/writing cp14 won't fault
the emulation.

Signed-off-by: Daniel Silverstone <dsilvers@simtec.co.uk>

 translate.c |   17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

=== modified file 'target-arm/translate.c'
--- target-arm/translate.c	2008-09-22 00:52:42 +0000
+++ target-arm/translate.c	2008-10-13 10:33:00 +0000
@@ -2643,6 +2643,19 @@
     return 0;
 }
 
+static int disas_cp14_insn(CPUState *env, DisasContext *s, uint32_t insn)
+{
+    uint32_t rd = (insn >> 12) & 0xf;
+    if (insn & (1<<20)) {
+        gen_op_movl_T0_im(0);
+        gen_movl_reg_T0(s, rd);
+    } else {
+        /* Nothing to do on writes to cp14 */
+    }
+    gen_lookup_tb(s);
+    return 0;
+}
+
 #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
 #define VFP_SREG(insn, bigbit, smallbit) \
   ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
@@ -5567,7 +5580,9 @@
 	return 1;
     case 10:
     case 11:
-	return disas_vfp_insn (env, s, insn);
+        return disas_vfp_insn (env, s, insn);
+    case 14:
+        return disas_cp14_insn (env, s, insn);
     case 15:
 	return disas_cp15_insn (env, s, insn);
     default: