From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KpKsm-0007JW-4s for qemu-devel@nongnu.org; Mon, 13 Oct 2008 06:42:36 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KpKsl-0007JE-Dn for qemu-devel@nongnu.org; Mon, 13 Oct 2008 06:42:35 -0400 Received: from [199.232.76.173] (port=47225 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KpKsl-0007J9-5n for qemu-devel@nongnu.org; Mon, 13 Oct 2008 06:42:35 -0400 Received: from batfish.pepperfish.net ([87.237.62.180]:33708 helo=flounder.pepperfish.net) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1KpKsk-0003hn-QF for qemu-devel@nongnu.org; Mon, 13 Oct 2008 06:42:35 -0400 Received: from cpc2-asht1-0-0-cust815.manc.cable.ntl.com ([80.5.55.48] helo=[10.19.3.101]) by flounder.pepperfish.net with esmtpsa (Exim 4.68 #1 (Debian)) id 1KpKsj-0006gH-3h for ; Mon, 13 Oct 2008 11:42:33 +0100 From: Daniel Silverstone Content-Type: multipart/mixed; boundary="=-I2zqzBfrjnFHQyQB/+Ii" Date: Mon, 13 Oct 2008 11:42:32 +0100 Message-Id: <1223894552.30000.30.camel@petitemort> Mime-Version: 1.0 Subject: [Qemu-devel] [PATCH] ARM CP14 trivial support Reply-To: dsilvers@simtec.co.uk, qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org --=-I2zqzBfrjnFHQyQB/+Ii Content-Type: text/plain Content-Transfer-Encoding: 7bit Hi, Continuing the patch series aiming at supporting Simtec's development boards and other Samsung SoC based systems, attached is a patch which provides trivial coprocessor 14 support. Regards, Daniel. -- Daniel Silverstone http://www.simtec.co.uk/ PGP mail accepted and encouraged. Key Id: 2BC8 4016 2068 7895 --=-I2zqzBfrjnFHQyQB/+Ii Content-Description: Trivial CP14 support patch Content-Disposition: inline; filename=cp14.patch Content-Type: text/x-patch; charset=UTF-8 Content-Transfer-Encoding: 7bit ARM9 CP14 support The ARM coprocessor number 14, in part, is responsible for describing CPU features. It is also the interface to the JTAG DCC channel which some systems use to control early-boot-time debugging. All this patch does is provide enough support that reading/writing cp14 won't fault the emulation. Signed-off-by: Daniel Silverstone translate.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) === modified file 'target-arm/translate.c' --- target-arm/translate.c 2008-09-22 00:52:42 +0000 +++ target-arm/translate.c 2008-10-13 10:33:00 +0000 @@ -2643,6 +2643,19 @@ return 0; } +static int disas_cp14_insn(CPUState *env, DisasContext *s, uint32_t insn) +{ + uint32_t rd = (insn >> 12) & 0xf; + if (insn & (1<<20)) { + gen_op_movl_T0_im(0); + gen_movl_reg_T0(s, rd); + } else { + /* Nothing to do on writes to cp14 */ + } + gen_lookup_tb(s); + return 0; +} + #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n)) #define VFP_SREG(insn, bigbit, smallbit) \ ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1)) @@ -5567,7 +5580,9 @@ return 1; case 10: case 11: - return disas_vfp_insn (env, s, insn); + return disas_vfp_insn (env, s, insn); + case 14: + return disas_cp14_insn (env, s, insn); case 15: return disas_cp15_insn (env, s, insn); default: --=-I2zqzBfrjnFHQyQB/+Ii--