From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KuuxB-0001BJ-Cy for qemu-devel@nongnu.org; Tue, 28 Oct 2008 16:14:13 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Kuux6-0001AT-Vq for qemu-devel@nongnu.org; Tue, 28 Oct 2008 16:14:13 -0400 Received: from [199.232.76.173] (port=34551 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Kuux6-0001AQ-PW for qemu-devel@nongnu.org; Tue, 28 Oct 2008 16:14:08 -0400 Received: from e38.co.us.ibm.com ([32.97.110.159]:56421) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Kuux6-0002EE-6B for qemu-devel@nongnu.org; Tue, 28 Oct 2008 16:14:09 -0400 Received: from d03relay04.boulder.ibm.com (d03relay04.boulder.ibm.com [9.17.195.106]) by e38.co.us.ibm.com (8.13.1/8.13.1) with ESMTP id m9SKD7GA016617 for ; Tue, 28 Oct 2008 14:13:07 -0600 Received: from d03av01.boulder.ibm.com (d03av01.boulder.ibm.com [9.17.195.167]) by d03relay04.boulder.ibm.com (8.13.8/8.13.8/NCO v9.1) with ESMTP id m9SKDeln062938 for ; Tue, 28 Oct 2008 14:13:40 -0600 Received: from d03av01.boulder.ibm.com (loopback [127.0.0.1]) by d03av01.boulder.ibm.com (8.12.11.20060308/8.13.3) with ESMTP id m9SKDdlg021045 for ; Tue, 28 Oct 2008 14:13:39 -0600 From: Anthony Liguori Date: Tue, 28 Oct 2008 15:13:32 -0500 Message-Id: <1225224814-9875-1-git-send-email-aliguori@us.ibm.com> Subject: [Qemu-devel] [PATCH 1/3] Add additional CPU flag definitions Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Glauber Costa , Avi Kivity , kvm-devel , Anthony Liguori Some x86 CPU definitions that KVM needs Signed-off-by: Anthony Liguori diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 3c11e0f..b1678ef 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -159,9 +159,11 @@ #define HF_MP_MASK (1 << HF_MP_SHIFT) #define HF_EM_MASK (1 << HF_EM_SHIFT) #define HF_TS_MASK (1 << HF_TS_SHIFT) +#define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) #define HF_LMA_MASK (1 << HF_LMA_SHIFT) #define HF_CS64_MASK (1 << HF_CS64_SHIFT) #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) +#define HF_VM_MASK (1 << HF_VM_SHIFT) #define HF_SMM_MASK (1 << HF_SMM_SHIFT) #define HF_SVME_MASK (1 << HF_SVME_SHIFT) #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT) @@ -178,6 +180,9 @@ #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) +#define CR0_PE_SHIFT 0 +#define CR0_MP_SHIFT 1 + #define CR0_PE_MASK (1 << 0) #define CR0_MP_MASK (1 << 1) #define CR0_EM_MASK (1 << 2) @@ -196,7 +201,8 @@ #define CR4_PAE_MASK (1 << 5) #define CR4_PGE_MASK (1 << 7) #define CR4_PCE_MASK (1 << 8) -#define CR4_OSFXSR_MASK (1 << 9) +#define CR4_OSFXSR_SHIFT 9 +#define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT) #define CR4_OSXMMEXCPT_MASK (1 << 10) #define PG_PRESENT_BIT 0 @@ -229,6 +235,7 @@ #define PG_ERROR_RSVD_MASK 0x08 #define PG_ERROR_I_D_MASK 0x10 +#define MSR_IA32_TSC 0x10 #define MSR_IA32_APICBASE 0x1b #define MSR_IA32_APICBASE_BSP (1<<8) #define MSR_IA32_APICBASE_ENABLE (1<<11)