From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1L3KAp-0006fo-4M for qemu-devel@nongnu.org; Thu, 20 Nov 2008 19:47:03 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1L3KAn-0006fF-Vh for qemu-devel@nongnu.org; Thu, 20 Nov 2008 19:47:02 -0500 Received: from [199.232.76.173] (port=58856 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1L3KAn-0006fB-Qh for qemu-devel@nongnu.org; Thu, 20 Nov 2008 19:47:01 -0500 Received: from agrajag.mansr.com ([78.86.181.102]:41742 helo=mail.mansr.com) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1L3KAn-0001S8-BC for qemu-devel@nongnu.org; Thu, 20 Nov 2008 19:47:01 -0500 Received: from thrashbarg.mansr.com (thrashbarg.mansr.com [78.86.181.100]) by mail.mansr.com (Postfix) with ESMTP id 2E5241C0089 for ; Fri, 21 Nov 2008 00:46:58 +0000 (GMT) From: Mans Rullgard Date: Fri, 21 Nov 2008 00:46:58 +0000 Message-Id: <1227228418-20118-1-git-send-email-mans@mansr.com> Subject: [Qemu-devel] [PATCH 1/2] target-sh4: fix 64-bit fmov to/from memory Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org When loading/storing a register pair, the even-numbered register always maps to the low 32 bits of memory independently of target endian configuration. Signed-off-by: Mans Rullgard --- target-sh4/translate.c | 63 ++++++++++++++++++++++++----------------------- 1 files changed, 32 insertions(+), 31 deletions(-) diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 84a3f40..5ce1a0d 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -991,31 +991,35 @@ static void _decode_opc(DisasContext * ctx) return; case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */ if (ctx->fpscr & FPSCR_SZ) { - TCGv_i64 fp = tcg_temp_new_i64(); - gen_load_fpr64(fp, XREG(B7_4)); - tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx); - tcg_temp_free_i64(fp); + TCGv fr = XREG(B7_4); + TCGv addr_hi = tcg_temp_new(); + tcg_gen_addi_i32(addr_hi, REG(B11_8), 4); + tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx); + tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx); + tcg_temp_free(addr_hi); } else { tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx); } return; case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */ if (ctx->fpscr & FPSCR_SZ) { - TCGv_i64 fp = tcg_temp_new_i64(); - tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx); - gen_store_fpr64(fp, XREG(B11_8)); - tcg_temp_free_i64(fp); + TCGv fr = XREG(B11_8); + TCGv addr_hi = tcg_temp_new(); + tcg_gen_addi_i32(addr_hi, REG(B7_4), 4); + tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx); + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx); + tcg_temp_free(addr_hi); } else { tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx); } return; case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */ if (ctx->fpscr & FPSCR_SZ) { - TCGv_i64 fp = tcg_temp_new_i64(); - tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx); - gen_store_fpr64(fp, XREG(B11_8)); - tcg_temp_free_i64(fp); - tcg_gen_addi_i32(REG(B7_4),REG(B7_4), 8); + int fr = XREG(B11_8); + tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx); + tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], REG(B7_4), ctx->memidx); + tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); } else { tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx); tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); @@ -1023,16 +1027,13 @@ static void _decode_opc(DisasContext * ctx) return; case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */ if (ctx->fpscr & FPSCR_SZ) { - TCGv addr; - TCGv_i64 fp; - addr = tcg_temp_new(); - tcg_gen_subi_i32(addr, REG(B11_8), 8); - fp = tcg_temp_new_i64(); - gen_load_fpr64(fp, XREG(B7_4)); - tcg_gen_qemu_st64(fp, addr, ctx->memidx); - tcg_temp_free_i64(fp); - tcg_temp_free(addr); - tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8); + TCGv addr = tcg_temp_new_i32(); + TCGv fr = XREG(B7_4); + tcg_gen_subi_i32(addr, REG(B11_8), 4); + tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8); + tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx); + tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx); + tcg_temp_free(addr); } else { TCGv addr; addr = tcg_temp_new_i32(); @@ -1047,10 +1048,10 @@ static void _decode_opc(DisasContext * ctx) TCGv addr = tcg_temp_new_i32(); tcg_gen_add_i32(addr, REG(B7_4), REG(0)); if (ctx->fpscr & FPSCR_SZ) { - TCGv_i64 fp = tcg_temp_new_i64(); - tcg_gen_qemu_ld64(fp, addr, ctx->memidx); - gen_store_fpr64(fp, XREG(B11_8)); - tcg_temp_free_i64(fp); + TCGv fr = XREG(B11_8); + tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx); + tcg_gen_add_i32(addr, addr, 4); + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx); } else { tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx); } @@ -1062,10 +1063,10 @@ static void _decode_opc(DisasContext * ctx) TCGv addr = tcg_temp_new(); tcg_gen_add_i32(addr, REG(B11_8), REG(0)); if (ctx->fpscr & FPSCR_SZ) { - TCGv_i64 fp = tcg_temp_new_i64(); - gen_load_fpr64(fp, XREG(B7_4)); - tcg_gen_qemu_st64(fp, addr, ctx->memidx); - tcg_temp_free_i64(fp); + TCGv fr = XREG(B7_4); + tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx); + tcg_gen_add_i32(addr, addr, 4); + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx); } else { tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx); } -- 1.6.0.4