* [Qemu-devel] [PATCH 1/2] target-sh4: fix 64-bit fmov to/from memory
@ 2008-11-21 0:46 Mans Rullgard
2008-11-21 19:56 ` [Qemu-devel] " Måns Rullgård
0 siblings, 1 reply; 4+ messages in thread
From: Mans Rullgard @ 2008-11-21 0:46 UTC (permalink / raw)
To: qemu-devel
When loading/storing a register pair, the even-numbered register
always maps to the low 32 bits of memory independently of target
endian configuration.
Signed-off-by: Mans Rullgard <mans@mansr.com>
---
target-sh4/translate.c | 63 ++++++++++++++++++++++++-----------------------
1 files changed, 32 insertions(+), 31 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 84a3f40..5ce1a0d 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -991,31 +991,35 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- gen_load_fpr64(fp, XREG(B7_4));
- tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx);
- tcg_temp_free_i64(fp);
+ TCGv fr = XREG(B7_4);
+ TCGv addr_hi = tcg_temp_new();
+ tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
+ tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
+ tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx);
+ tcg_temp_free(addr_hi);
} else {
tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx);
}
return;
case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
- gen_store_fpr64(fp, XREG(B11_8));
- tcg_temp_free_i64(fp);
+ TCGv fr = XREG(B11_8);
+ TCGv addr_hi = tcg_temp_new();
+ tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
+ tcg_temp_free(addr_hi);
} else {
tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
}
return;
case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
- gen_store_fpr64(fp, XREG(B11_8));
- tcg_temp_free_i64(fp);
- tcg_gen_addi_i32(REG(B7_4),REG(B7_4), 8);
+ int fr = XREG(B11_8);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
+ tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], REG(B7_4), ctx->memidx);
+ tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
} else {
tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
@@ -1023,16 +1027,13 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- TCGv addr;
- TCGv_i64 fp;
- addr = tcg_temp_new();
- tcg_gen_subi_i32(addr, REG(B11_8), 8);
- fp = tcg_temp_new_i64();
- gen_load_fpr64(fp, XREG(B7_4));
- tcg_gen_qemu_st64(fp, addr, ctx->memidx);
- tcg_temp_free_i64(fp);
- tcg_temp_free(addr);
- tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
+ TCGv addr = tcg_temp_new_i32();
+ TCGv fr = XREG(B7_4);
+ tcg_gen_subi_i32(addr, REG(B11_8), 4);
+ tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
+ tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
+ tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx);
+ tcg_temp_free(addr);
} else {
TCGv addr;
addr = tcg_temp_new_i32();
@@ -1047,10 +1048,10 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new_i32();
tcg_gen_add_i32(addr, REG(B7_4), REG(0));
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(fp, addr, ctx->memidx);
- gen_store_fpr64(fp, XREG(B11_8));
- tcg_temp_free_i64(fp);
+ TCGv fr = XREG(B11_8);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
+ tcg_gen_add_i32(addr, addr, 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
} else {
tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx);
}
@@ -1062,10 +1063,10 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B11_8), REG(0));
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- gen_load_fpr64(fp, XREG(B7_4));
- tcg_gen_qemu_st64(fp, addr, ctx->memidx);
- tcg_temp_free_i64(fp);
+ TCGv fr = XREG(B7_4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
+ tcg_gen_add_i32(addr, addr, 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
} else {
tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
}
--
1.6.0.4
^ permalink raw reply related [flat|nested] 4+ messages in thread* [Qemu-devel] [PATCH 1/2] target-sh4: fix 64-bit fmov to/from memory
@ 2008-11-21 19:55 Mans Rullgard
2008-11-21 20:38 ` Aurelien Jarno
0 siblings, 1 reply; 4+ messages in thread
From: Mans Rullgard @ 2008-11-21 19:55 UTC (permalink / raw)
To: qemu-devel
When loading/storing a register pair, the even-numbered register
always maps to the low 32 bits of memory independently of target
endian configuration.
Signed-off-by: Mans Rullgard <mans@mansr.com>
---
target-sh4/translate.c | 63 ++++++++++++++++++++++++-----------------------
1 files changed, 32 insertions(+), 31 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 84a3f40..2d6dfe6 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -991,31 +991,35 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- gen_load_fpr64(fp, XREG(B7_4));
- tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx);
- tcg_temp_free_i64(fp);
+ TCGv addr_hi = tcg_temp_new();
+ int fr = XREG(B7_4);
+ tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
+ tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
+ tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx);
+ tcg_temp_free(addr_hi);
} else {
tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx);
}
return;
case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
- gen_store_fpr64(fp, XREG(B11_8));
- tcg_temp_free_i64(fp);
+ TCGv addr_hi = tcg_temp_new();
+ int fr = XREG(B11_8);
+ tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
+ tcg_temp_free(addr_hi);
} else {
tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
}
return;
case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
- gen_store_fpr64(fp, XREG(B11_8));
- tcg_temp_free_i64(fp);
- tcg_gen_addi_i32(REG(B7_4),REG(B7_4), 8);
+ int fr = XREG(B11_8);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
+ tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], REG(B7_4), ctx->memidx);
+ tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
} else {
tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
@@ -1023,16 +1027,13 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- TCGv addr;
- TCGv_i64 fp;
- addr = tcg_temp_new();
- tcg_gen_subi_i32(addr, REG(B11_8), 8);
- fp = tcg_temp_new_i64();
- gen_load_fpr64(fp, XREG(B7_4));
- tcg_gen_qemu_st64(fp, addr, ctx->memidx);
- tcg_temp_free_i64(fp);
- tcg_temp_free(addr);
- tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
+ TCGv addr = tcg_temp_new_i32();
+ int fr = XREG(B7_4);
+ tcg_gen_subi_i32(addr, REG(B11_8), 4);
+ tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
+ tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
+ tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx);
+ tcg_temp_free(addr);
} else {
TCGv addr;
addr = tcg_temp_new_i32();
@@ -1047,10 +1048,10 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new_i32();
tcg_gen_add_i32(addr, REG(B7_4), REG(0));
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(fp, addr, ctx->memidx);
- gen_store_fpr64(fp, XREG(B11_8));
- tcg_temp_free_i64(fp);
+ int fr = XREG(B11_8);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
+ tcg_gen_addi_i32(addr, addr, 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
} else {
tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx);
}
@@ -1062,10 +1063,10 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B11_8), REG(0));
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- gen_load_fpr64(fp, XREG(B7_4));
- tcg_gen_qemu_st64(fp, addr, ctx->memidx);
- tcg_temp_free_i64(fp);
+ int fr = XREG(B7_4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
+ tcg_gen_addi_i32(addr, addr, 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
} else {
tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
}
--
1.6.0.4
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [Qemu-devel] [PATCH 1/2] target-sh4: fix 64-bit fmov to/from memory
2008-11-21 19:55 [Qemu-devel] " Mans Rullgard
@ 2008-11-21 20:38 ` Aurelien Jarno
0 siblings, 0 replies; 4+ messages in thread
From: Aurelien Jarno @ 2008-11-21 20:38 UTC (permalink / raw)
To: qemu-devel
On Fri, Nov 21, 2008 at 07:55:41PM +0000, Mans Rullgard wrote:
> When loading/storing a register pair, the even-numbered register
> always maps to the low 32 bits of memory independently of target
> endian configuration.
>
> Signed-off-by: Mans Rullgard <mans@mansr.com>
> ---
> target-sh4/translate.c | 63 ++++++++++++++++++++++++-----------------------
> 1 files changed, 32 insertions(+), 31 deletions(-)
>
> diff --git a/target-sh4/translate.c b/target-sh4/translate.c
> index 84a3f40..2d6dfe6 100644
> --- a/target-sh4/translate.c
> +++ b/target-sh4/translate.c
> @@ -991,31 +991,35 @@ static void _decode_opc(DisasContext * ctx)
> return;
> case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv_i64 fp = tcg_temp_new_i64();
> - gen_load_fpr64(fp, XREG(B7_4));
> - tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx);
> - tcg_temp_free_i64(fp);
> + TCGv addr_hi = tcg_temp_new();
> + int fr = XREG(B7_4);
> + tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
> + tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
> + tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx);
> + tcg_temp_free(addr_hi);
You are totally breaking the indendation. Care to resend this patch with
a proper indentation?
> } else {
> tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx);
> }
> return;
> case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv_i64 fp = tcg_temp_new_i64();
> - tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
> - gen_store_fpr64(fp, XREG(B11_8));
> - tcg_temp_free_i64(fp);
> + TCGv addr_hi = tcg_temp_new();
> + int fr = XREG(B11_8);
> + tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
> + tcg_temp_free(addr_hi);
> } else {
> tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
> }
> return;
> case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv_i64 fp = tcg_temp_new_i64();
> - tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
> - gen_store_fpr64(fp, XREG(B11_8));
> - tcg_temp_free_i64(fp);
> - tcg_gen_addi_i32(REG(B7_4),REG(B7_4), 8);
> + int fr = XREG(B11_8);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
> + tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], REG(B7_4), ctx->memidx);
> + tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
> } else {
> tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
> tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
> @@ -1023,16 +1027,13 @@ static void _decode_opc(DisasContext * ctx)
> return;
> case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv addr;
> - TCGv_i64 fp;
> - addr = tcg_temp_new();
> - tcg_gen_subi_i32(addr, REG(B11_8), 8);
> - fp = tcg_temp_new_i64();
> - gen_load_fpr64(fp, XREG(B7_4));
> - tcg_gen_qemu_st64(fp, addr, ctx->memidx);
> - tcg_temp_free_i64(fp);
> - tcg_temp_free(addr);
> - tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
> + TCGv addr = tcg_temp_new_i32();
> + int fr = XREG(B7_4);
> + tcg_gen_subi_i32(addr, REG(B11_8), 4);
> + tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
> + tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
> + tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx);
> + tcg_temp_free(addr);
> } else {
> TCGv addr;
> addr = tcg_temp_new_i32();
> @@ -1047,10 +1048,10 @@ static void _decode_opc(DisasContext * ctx)
> TCGv addr = tcg_temp_new_i32();
> tcg_gen_add_i32(addr, REG(B7_4), REG(0));
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv_i64 fp = tcg_temp_new_i64();
> - tcg_gen_qemu_ld64(fp, addr, ctx->memidx);
> - gen_store_fpr64(fp, XREG(B11_8));
> - tcg_temp_free_i64(fp);
> + int fr = XREG(B11_8);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
> + tcg_gen_addi_i32(addr, addr, 4);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
> } else {
> tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx);
> }
> @@ -1062,10 +1063,10 @@ static void _decode_opc(DisasContext * ctx)
> TCGv addr = tcg_temp_new();
> tcg_gen_add_i32(addr, REG(B11_8), REG(0));
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv_i64 fp = tcg_temp_new_i64();
> - gen_load_fpr64(fp, XREG(B7_4));
> - tcg_gen_qemu_st64(fp, addr, ctx->memidx);
> - tcg_temp_free_i64(fp);
> + int fr = XREG(B7_4);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
> + tcg_gen_addi_i32(addr, addr, 4);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
> } else {
> tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
> }
> --
> 1.6.0.4
>
>
>
>
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 4+ messages in thread
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2008-11-21 20:38 ` Aurelien Jarno
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