[Qemu-devel] [PATCH 2/2] target-sh4: implement ftrv instruction

[Mans Rullgard <mans@mansr.com>]

This partially implements the ftrv instruction.  It gives correct
results under normal conditions.  FPU exceptions are not correctly
generated.

Signed-off-by: Mans Rullgard <mans@mansr.com>
---
 target-sh4/translate.c |   32 ++++++++++++++++++++++++++++++++
 1 files changed, 32 insertions(+), 0 deletions(-)

diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 5ce1a0d..9371f0d 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -1694,6 +1694,38 @@ static void _decode_opc(DisasContext * ctx)
 	    tcg_temp_free_i64(fp);
 	}
 	return;
+    case 0xf0fd: /* ftrv XMTRX,FVn */
+        if ((ctx->opcode & 0x300) != 0x100)
+            break;
+        if (!(ctx->fpscr & FPSCR_PR)) {
+            TCGv fv[4];
+            TCGv fp;
+            int n = B11_8 & 0xc;
+            int i;
+
+            fp = tcg_temp_new();
+
+            for (i = 0; i < 4; i++) {
+                fv[i] = tcg_temp_new();
+                tcg_gen_mov_i32(fv[i], cpu_fregs[n+i]);
+            }
+
+            for (i = 0; i < 4; i++) {
+                gen_helper_fmul_FT(cpu_fregs[n+i], cpu_fregs[16+i], fv[0]);
+                gen_helper_fmul_FT(fp,             cpu_fregs[20+i], fv[1]);
+                gen_helper_fadd_FT(cpu_fregs[n+i], cpu_fregs[n+i],  fp);
+                gen_helper_fmul_FT(fp,             cpu_fregs[24+i], fv[2]);
+                gen_helper_fadd_FT(cpu_fregs[n+i], cpu_fregs[n+i],  fp);
+                gen_helper_fmul_FT(fp,             cpu_fregs[28+i], fv[3]);
+                gen_helper_fadd_FT(cpu_fregs[n+i], cpu_fregs[n+i],  fp);
+            }
+
+            for (i = 0; i < 4; i++)
+                tcg_temp_free(fv[i]);
+            tcg_temp_free(fp);
+            return;
+        }
+        break;
     }
 
     fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n",
-- 
1.6.0.4