* [Qemu-devel] [PATCH 1/2] target-sh4: fix 64-bit fmov to/from memory
@ 2008-11-21 19:55 Mans Rullgard
2008-11-21 19:55 ` [Qemu-devel] [PATCH 2/2] target-sh4: implement ftrv instruction Mans Rullgard
2008-11-21 20:38 ` [Qemu-devel] [PATCH 1/2] target-sh4: fix 64-bit fmov to/from memory Aurelien Jarno
0 siblings, 2 replies; 14+ messages in thread
From: Mans Rullgard @ 2008-11-21 19:55 UTC (permalink / raw)
To: qemu-devel
When loading/storing a register pair, the even-numbered register
always maps to the low 32 bits of memory independently of target
endian configuration.
Signed-off-by: Mans Rullgard <mans@mansr.com>
---
target-sh4/translate.c | 63 ++++++++++++++++++++++++-----------------------
1 files changed, 32 insertions(+), 31 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 84a3f40..2d6dfe6 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -991,31 +991,35 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- gen_load_fpr64(fp, XREG(B7_4));
- tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx);
- tcg_temp_free_i64(fp);
+ TCGv addr_hi = tcg_temp_new();
+ int fr = XREG(B7_4);
+ tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
+ tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
+ tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx);
+ tcg_temp_free(addr_hi);
} else {
tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx);
}
return;
case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
- gen_store_fpr64(fp, XREG(B11_8));
- tcg_temp_free_i64(fp);
+ TCGv addr_hi = tcg_temp_new();
+ int fr = XREG(B11_8);
+ tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
+ tcg_temp_free(addr_hi);
} else {
tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
}
return;
case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
- gen_store_fpr64(fp, XREG(B11_8));
- tcg_temp_free_i64(fp);
- tcg_gen_addi_i32(REG(B7_4),REG(B7_4), 8);
+ int fr = XREG(B11_8);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
+ tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], REG(B7_4), ctx->memidx);
+ tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
} else {
tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
@@ -1023,16 +1027,13 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- TCGv addr;
- TCGv_i64 fp;
- addr = tcg_temp_new();
- tcg_gen_subi_i32(addr, REG(B11_8), 8);
- fp = tcg_temp_new_i64();
- gen_load_fpr64(fp, XREG(B7_4));
- tcg_gen_qemu_st64(fp, addr, ctx->memidx);
- tcg_temp_free_i64(fp);
- tcg_temp_free(addr);
- tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
+ TCGv addr = tcg_temp_new_i32();
+ int fr = XREG(B7_4);
+ tcg_gen_subi_i32(addr, REG(B11_8), 4);
+ tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
+ tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
+ tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx);
+ tcg_temp_free(addr);
} else {
TCGv addr;
addr = tcg_temp_new_i32();
@@ -1047,10 +1048,10 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new_i32();
tcg_gen_add_i32(addr, REG(B7_4), REG(0));
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(fp, addr, ctx->memidx);
- gen_store_fpr64(fp, XREG(B11_8));
- tcg_temp_free_i64(fp);
+ int fr = XREG(B11_8);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
+ tcg_gen_addi_i32(addr, addr, 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
} else {
tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx);
}
@@ -1062,10 +1063,10 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B11_8), REG(0));
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- gen_load_fpr64(fp, XREG(B7_4));
- tcg_gen_qemu_st64(fp, addr, ctx->memidx);
- tcg_temp_free_i64(fp);
+ int fr = XREG(B7_4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
+ tcg_gen_addi_i32(addr, addr, 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
} else {
tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
}
--
1.6.0.4
^ permalink raw reply related [flat|nested] 14+ messages in thread* [Qemu-devel] [PATCH 2/2] target-sh4: implement ftrv instruction
2008-11-21 19:55 [Qemu-devel] [PATCH 1/2] target-sh4: fix 64-bit fmov to/from memory Mans Rullgard
@ 2008-11-21 19:55 ` Mans Rullgard
2009-02-03 20:28 ` Aurelien Jarno
2008-11-21 20:38 ` [Qemu-devel] [PATCH 1/2] target-sh4: fix 64-bit fmov to/from memory Aurelien Jarno
1 sibling, 1 reply; 14+ messages in thread
From: Mans Rullgard @ 2008-11-21 19:55 UTC (permalink / raw)
To: qemu-devel
This partially implements the ftrv instruction. It gives correct
results under normal conditions. FPU exceptions are not correctly
generated.
Signed-off-by: Mans Rullgard <mans@mansr.com>
---
target-sh4/translate.c | 40 ++++++++++++++++++++++++++++++++++++++++
1 files changed, 40 insertions(+), 0 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 2d6dfe6..9c2da41 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -1694,6 +1694,46 @@ static void _decode_opc(DisasContext * ctx)
tcg_temp_free_i64(fp);
}
return;
+ case 0xf0fd: /* ftrv XMTRX,FVn */
+ if ((ctx->opcode & 0x300) != 0x100)
+ break;
+ if (!(ctx->fpscr & FPSCR_PR)) {
+ TCGv fv[4];
+ TCGv fp;
+ int n = B11_8 & 0xc;
+ int i;
+
+ /*
+ * NOTE: The values calculated here are likely to differ
+ * from hardware since the hardware sacrifices accuracy
+ * for speed in this instruction.
+ *
+ * FIXME: FPU exceptions are not correctly raised here.
+ */
+
+ fp = tcg_temp_new();
+
+ for (i = 0; i < 4; i++) {
+ fv[i] = tcg_temp_new();
+ tcg_gen_mov_i32(fv[i], cpu_fregs[n+i]);
+ }
+
+ for (i = 0; i < 4; i++) {
+ gen_helper_fmul_FT(cpu_fregs[n+i], cpu_fregs[16+i], fv[0]);
+ gen_helper_fmul_FT(fp, cpu_fregs[20+i], fv[1]);
+ gen_helper_fadd_FT(cpu_fregs[n+i], cpu_fregs[n+i], fp);
+ gen_helper_fmul_FT(fp, cpu_fregs[24+i], fv[2]);
+ gen_helper_fadd_FT(cpu_fregs[n+i], cpu_fregs[n+i], fp);
+ gen_helper_fmul_FT(fp, cpu_fregs[28+i], fv[3]);
+ gen_helper_fadd_FT(cpu_fregs[n+i], cpu_fregs[n+i], fp);
+ }
+
+ for (i = 0; i < 4; i++)
+ tcg_temp_free(fv[i]);
+ tcg_temp_free(fp);
+ return;
+ }
+ break;
}
fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n",
--
1.6.0.4
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [Qemu-devel] [PATCH 2/2] target-sh4: implement ftrv instruction
2008-11-21 19:55 ` [Qemu-devel] [PATCH 2/2] target-sh4: implement ftrv instruction Mans Rullgard
@ 2009-02-03 20:28 ` Aurelien Jarno
0 siblings, 0 replies; 14+ messages in thread
From: Aurelien Jarno @ 2009-02-03 20:28 UTC (permalink / raw)
To: Mans Rullgard; +Cc: qemu-devel
On Fri, Nov 21, 2008 at 07:55:42PM +0000, Mans Rullgard wrote:
> This partially implements the ftrv instruction. It gives correct
> results under normal conditions. FPU exceptions are not correctly
> generated.
>
> Signed-off-by: Mans Rullgard <mans@mansr.com>
> ---
> target-sh4/translate.c | 40 ++++++++++++++++++++++++++++++++++++++++
> 1 files changed, 40 insertions(+), 0 deletions(-)
>
> diff --git a/target-sh4/translate.c b/target-sh4/translate.c
> index 2d6dfe6..9c2da41 100644
> --- a/target-sh4/translate.c
> +++ b/target-sh4/translate.c
> @@ -1694,6 +1694,46 @@ static void _decode_opc(DisasContext * ctx)
> tcg_temp_free_i64(fp);
> }
> return;
> + case 0xf0fd: /* ftrv XMTRX,FVn */
> + if ((ctx->opcode & 0x300) != 0x100)
> + break;
> + if (!(ctx->fpscr & FPSCR_PR)) {
> + TCGv fv[4];
> + TCGv fp;
> + int n = B11_8 & 0xc;
> + int i;
> +
> + /*
> + * NOTE: The values calculated here are likely to differ
> + * from hardware since the hardware sacrifices accuracy
> + * for speed in this instruction.
> + *
> + * FIXME: FPU exceptions are not correctly raised here.
> + */
> +
> + fp = tcg_temp_new();
> +
> + for (i = 0; i < 4; i++) {
> + fv[i] = tcg_temp_new();
> + tcg_gen_mov_i32(fv[i], cpu_fregs[n+i]);
> + }
> +
> + for (i = 0; i < 4; i++) {
> + gen_helper_fmul_FT(cpu_fregs[n+i], cpu_fregs[16+i], fv[0]);
> + gen_helper_fmul_FT(fp, cpu_fregs[20+i], fv[1]);
> + gen_helper_fadd_FT(cpu_fregs[n+i], cpu_fregs[n+i], fp);
> + gen_helper_fmul_FT(fp, cpu_fregs[24+i], fv[2]);
> + gen_helper_fadd_FT(cpu_fregs[n+i], cpu_fregs[n+i], fp);
> + gen_helper_fmul_FT(fp, cpu_fregs[28+i], fv[3]);
> + gen_helper_fadd_FT(cpu_fregs[n+i], cpu_fregs[n+i], fp);
> + }
> +
> + for (i = 0; i < 4; i++)
> + tcg_temp_free(fv[i]);
> + tcg_temp_free(fp);
> + return;
> + }
> + break;
> }
>
> fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n",
While this code probably produce the correct result, I am not sure it is
the best way to do it. It calls 28 times an helper, and uses 5 temp
variable. IMHO the ftrv should be implemented in an helper, called from
translate.c.
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH 1/2] target-sh4: fix 64-bit fmov to/from memory
2008-11-21 19:55 [Qemu-devel] [PATCH 1/2] target-sh4: fix 64-bit fmov to/from memory Mans Rullgard
2008-11-21 19:55 ` [Qemu-devel] [PATCH 2/2] target-sh4: implement ftrv instruction Mans Rullgard
@ 2008-11-21 20:38 ` Aurelien Jarno
2008-11-21 21:24 ` [Qemu-devel] " Måns Rullgård
1 sibling, 1 reply; 14+ messages in thread
From: Aurelien Jarno @ 2008-11-21 20:38 UTC (permalink / raw)
To: qemu-devel
On Fri, Nov 21, 2008 at 07:55:41PM +0000, Mans Rullgard wrote:
> When loading/storing a register pair, the even-numbered register
> always maps to the low 32 bits of memory independently of target
> endian configuration.
>
> Signed-off-by: Mans Rullgard <mans@mansr.com>
> ---
> target-sh4/translate.c | 63 ++++++++++++++++++++++++-----------------------
> 1 files changed, 32 insertions(+), 31 deletions(-)
>
> diff --git a/target-sh4/translate.c b/target-sh4/translate.c
> index 84a3f40..2d6dfe6 100644
> --- a/target-sh4/translate.c
> +++ b/target-sh4/translate.c
> @@ -991,31 +991,35 @@ static void _decode_opc(DisasContext * ctx)
> return;
> case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv_i64 fp = tcg_temp_new_i64();
> - gen_load_fpr64(fp, XREG(B7_4));
> - tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx);
> - tcg_temp_free_i64(fp);
> + TCGv addr_hi = tcg_temp_new();
> + int fr = XREG(B7_4);
> + tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
> + tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
> + tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx);
> + tcg_temp_free(addr_hi);
You are totally breaking the indendation. Care to resend this patch with
a proper indentation?
> } else {
> tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx);
> }
> return;
> case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv_i64 fp = tcg_temp_new_i64();
> - tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
> - gen_store_fpr64(fp, XREG(B11_8));
> - tcg_temp_free_i64(fp);
> + TCGv addr_hi = tcg_temp_new();
> + int fr = XREG(B11_8);
> + tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
> + tcg_temp_free(addr_hi);
> } else {
> tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
> }
> return;
> case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv_i64 fp = tcg_temp_new_i64();
> - tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
> - gen_store_fpr64(fp, XREG(B11_8));
> - tcg_temp_free_i64(fp);
> - tcg_gen_addi_i32(REG(B7_4),REG(B7_4), 8);
> + int fr = XREG(B11_8);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
> + tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], REG(B7_4), ctx->memidx);
> + tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
> } else {
> tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
> tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
> @@ -1023,16 +1027,13 @@ static void _decode_opc(DisasContext * ctx)
> return;
> case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv addr;
> - TCGv_i64 fp;
> - addr = tcg_temp_new();
> - tcg_gen_subi_i32(addr, REG(B11_8), 8);
> - fp = tcg_temp_new_i64();
> - gen_load_fpr64(fp, XREG(B7_4));
> - tcg_gen_qemu_st64(fp, addr, ctx->memidx);
> - tcg_temp_free_i64(fp);
> - tcg_temp_free(addr);
> - tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
> + TCGv addr = tcg_temp_new_i32();
> + int fr = XREG(B7_4);
> + tcg_gen_subi_i32(addr, REG(B11_8), 4);
> + tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
> + tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
> + tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx);
> + tcg_temp_free(addr);
> } else {
> TCGv addr;
> addr = tcg_temp_new_i32();
> @@ -1047,10 +1048,10 @@ static void _decode_opc(DisasContext * ctx)
> TCGv addr = tcg_temp_new_i32();
> tcg_gen_add_i32(addr, REG(B7_4), REG(0));
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv_i64 fp = tcg_temp_new_i64();
> - tcg_gen_qemu_ld64(fp, addr, ctx->memidx);
> - gen_store_fpr64(fp, XREG(B11_8));
> - tcg_temp_free_i64(fp);
> + int fr = XREG(B11_8);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
> + tcg_gen_addi_i32(addr, addr, 4);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
> } else {
> tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx);
> }
> @@ -1062,10 +1063,10 @@ static void _decode_opc(DisasContext * ctx)
> TCGv addr = tcg_temp_new();
> tcg_gen_add_i32(addr, REG(B11_8), REG(0));
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv_i64 fp = tcg_temp_new_i64();
> - gen_load_fpr64(fp, XREG(B7_4));
> - tcg_gen_qemu_st64(fp, addr, ctx->memidx);
> - tcg_temp_free_i64(fp);
> + int fr = XREG(B7_4);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
> + tcg_gen_addi_i32(addr, addr, 4);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
> } else {
> tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
> }
> --
> 1.6.0.4
>
>
>
>
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 14+ messages in thread* [Qemu-devel] Re: [PATCH 1/2] target-sh4: fix 64-bit fmov to/from memory
2008-11-21 20:38 ` [Qemu-devel] [PATCH 1/2] target-sh4: fix 64-bit fmov to/from memory Aurelien Jarno
@ 2008-11-21 21:24 ` Måns Rullgård
2008-11-21 21:46 ` Aurelien Jarno
0 siblings, 1 reply; 14+ messages in thread
From: Måns Rullgård @ 2008-11-21 21:24 UTC (permalink / raw)
To: qemu-devel
Aurelien Jarno <aurelien@aurel32.net> writes:
> On Fri, Nov 21, 2008 at 07:55:41PM +0000, Mans Rullgard wrote:
>> When loading/storing a register pair, the even-numbered register
>> always maps to the low 32 bits of memory independently of target
>> endian configuration.
>>
>> Signed-off-by: Mans Rullgard <mans@mansr.com>
>> ---
>> target-sh4/translate.c | 63 ++++++++++++++++++++++++-----------------------
>> 1 files changed, 32 insertions(+), 31 deletions(-)
>>
>> diff --git a/target-sh4/translate.c b/target-sh4/translate.c
>> index 84a3f40..2d6dfe6 100644
>> --- a/target-sh4/translate.c
>> +++ b/target-sh4/translate.c
>> @@ -991,31 +991,35 @@ static void _decode_opc(DisasContext * ctx)
>> return;
>> case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
>> if (ctx->fpscr & FPSCR_SZ) {
>> - TCGv_i64 fp = tcg_temp_new_i64();
>> - gen_load_fpr64(fp, XREG(B7_4));
>> - tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx);
>> - tcg_temp_free_i64(fp);
>> + TCGv addr_hi = tcg_temp_new();
>> + int fr = XREG(B7_4);
>> + tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
>> + tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
>> + tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx);
>> + tcg_temp_free(addr_hi);
>
> You are totally breaking the indendation. Care to resend this patch with
> a proper indentation?
I was told to use spaces for indentation even if surrounding code uses
tabs. I'll be happy to convert it to tabs if that's what you want.
--
Måns Rullgård
mans@mansr.com
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [Qemu-devel] Re: [PATCH 1/2] target-sh4: fix 64-bit fmov to/from memory
2008-11-21 21:24 ` [Qemu-devel] " Måns Rullgård
@ 2008-11-21 21:46 ` Aurelien Jarno
2008-11-21 22:23 ` [Qemu-devel] [PATCH] " Mans Rullgard
2008-11-21 22:25 ` [Qemu-devel] Re: [PATCH 1/2] " Måns Rullgård
0 siblings, 2 replies; 14+ messages in thread
From: Aurelien Jarno @ 2008-11-21 21:46 UTC (permalink / raw)
To: qemu-devel
On Fri, Nov 21, 2008 at 09:24:03PM +0000, Måns Rullgård wrote:
> Aurelien Jarno <aurelien@aurel32.net> writes:
>
> > On Fri, Nov 21, 2008 at 07:55:41PM +0000, Mans Rullgard wrote:
> >> When loading/storing a register pair, the even-numbered register
> >> always maps to the low 32 bits of memory independently of target
> >> endian configuration.
> >>
> >> Signed-off-by: Mans Rullgard <mans@mansr.com>
> >> ---
> >> target-sh4/translate.c | 63 ++++++++++++++++++++++++-----------------------
> >> 1 files changed, 32 insertions(+), 31 deletions(-)
> >>
> >> diff --git a/target-sh4/translate.c b/target-sh4/translate.c
> >> index 84a3f40..2d6dfe6 100644
> >> --- a/target-sh4/translate.c
> >> +++ b/target-sh4/translate.c
> >> @@ -991,31 +991,35 @@ static void _decode_opc(DisasContext * ctx)
> >> return;
> >> case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
> >> if (ctx->fpscr & FPSCR_SZ) {
> >> - TCGv_i64 fp = tcg_temp_new_i64();
> >> - gen_load_fpr64(fp, XREG(B7_4));
> >> - tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx);
> >> - tcg_temp_free_i64(fp);
> >> + TCGv addr_hi = tcg_temp_new();
> >> + int fr = XREG(B7_4);
> >> + tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
> >> + tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
> >> + tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx);
> >> + tcg_temp_free(addr_hi);
> >
> > You are totally breaking the indendation. Care to resend this patch with
> > a proper indentation?
>
> I was told to use spaces for indentation even if surrounding code uses
> tabs. I'll be happy to convert it to tabs if that's what you want.
>
The current file use tabs. While it is not consistent with other qemu
files, I think mixed indentation is even worse.
Please use tabs in your patch, and if you really like to you can send a
patch to convert the indentation of the whole file to spaces, but please
do it in a separate patch.
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 14+ messages in thread* [Qemu-devel] [PATCH] target-sh4: fix 64-bit fmov to/from memory
2008-11-21 21:46 ` Aurelien Jarno
@ 2008-11-21 22:23 ` Mans Rullgard
2008-11-21 23:02 ` Aurelien Jarno
2008-11-21 22:25 ` [Qemu-devel] Re: [PATCH 1/2] " Måns Rullgård
1 sibling, 1 reply; 14+ messages in thread
From: Mans Rullgard @ 2008-11-21 22:23 UTC (permalink / raw)
To: qemu-devel
When loading/storing a register pair, the even-numbered register
always maps to the low 32 bits of memory independently of target
endian configuration.
Signed-off-by: Mans Rullgard <mans@mansr.com>
---
target-sh4/translate.c | 61 ++++++++++++++++++++++++-----------------------
1 files changed, 31 insertions(+), 30 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 84a3f40..74894e9 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -991,31 +991,35 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- gen_load_fpr64(fp, XREG(B7_4));
- tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx);
- tcg_temp_free_i64(fp);
+ TCGv addr_hi = tcg_temp_new();
+ int fr = XREG(B7_4);
+ tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
+ tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
+ tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx);
+ tcg_temp_free(addr_hi);
} else {
tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx);
}
return;
case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
- gen_store_fpr64(fp, XREG(B11_8));
- tcg_temp_free_i64(fp);
+ TCGv addr_hi = tcg_temp_new();
+ int fr = XREG(B11_8);
+ tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
+ tcg_temp_free(addr_hi);
} else {
tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
}
return;
case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
- gen_store_fpr64(fp, XREG(B11_8));
- tcg_temp_free_i64(fp);
- tcg_gen_addi_i32(REG(B7_4),REG(B7_4), 8);
+ int fr = XREG(B11_8);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
+ tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], REG(B7_4), ctx->memidx);
+ tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
} else {
tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
@@ -1023,16 +1027,13 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- TCGv addr;
- TCGv_i64 fp;
- addr = tcg_temp_new();
- tcg_gen_subi_i32(addr, REG(B11_8), 8);
- fp = tcg_temp_new_i64();
- gen_load_fpr64(fp, XREG(B7_4));
- tcg_gen_qemu_st64(fp, addr, ctx->memidx);
- tcg_temp_free_i64(fp);
- tcg_temp_free(addr);
+ TCGv addr = tcg_temp_new_i32();
+ int fr = XREG(B7_4);
+ tcg_gen_subi_i32(addr, REG(B11_8), 4);
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
+ tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
+ tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx);
+ tcg_temp_free(addr);
} else {
TCGv addr;
addr = tcg_temp_new_i32();
@@ -1047,10 +1048,10 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new_i32();
tcg_gen_add_i32(addr, REG(B7_4), REG(0));
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(fp, addr, ctx->memidx);
- gen_store_fpr64(fp, XREG(B11_8));
- tcg_temp_free_i64(fp);
+ int fr = XREG(B11_8);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
+ tcg_gen_addi_i32(addr, addr, 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
} else {
tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx);
}
@@ -1062,10 +1063,10 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B11_8), REG(0));
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- gen_load_fpr64(fp, XREG(B7_4));
- tcg_gen_qemu_st64(fp, addr, ctx->memidx);
- tcg_temp_free_i64(fp);
+ int fr = XREG(B7_4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
+ tcg_gen_addi_i32(addr, addr, 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
} else {
tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
}
--
1.6.0.4
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [Qemu-devel] [PATCH] target-sh4: fix 64-bit fmov to/from memory
2008-11-21 22:23 ` [Qemu-devel] [PATCH] " Mans Rullgard
@ 2008-11-21 23:02 ` Aurelien Jarno
2008-11-21 23:30 ` [Qemu-devel] " Måns Rullgård
0 siblings, 1 reply; 14+ messages in thread
From: Aurelien Jarno @ 2008-11-21 23:02 UTC (permalink / raw)
To: qemu-devel
On Fri, Nov 21, 2008 at 10:23:54PM +0000, Mans Rullgard wrote:
> When loading/storing a register pair, the even-numbered register
> always maps to the low 32 bits of memory independently of target
> endian configuration.
>
> Signed-off-by: Mans Rullgard <mans@mansr.com>
> ---
> target-sh4/translate.c | 61 ++++++++++++++++++++++++-----------------------
> 1 files changed, 31 insertions(+), 30 deletions(-)
>
> diff --git a/target-sh4/translate.c b/target-sh4/translate.c
> index 84a3f40..74894e9 100644
> --- a/target-sh4/translate.c
> +++ b/target-sh4/translate.c
> @@ -991,31 +991,35 @@ static void _decode_opc(DisasContext * ctx)
> return;
> case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv_i64 fp = tcg_temp_new_i64();
> - gen_load_fpr64(fp, XREG(B7_4));
> - tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx);
> - tcg_temp_free_i64(fp);
> + TCGv addr_hi = tcg_temp_new();
> + int fr = XREG(B7_4);
> + tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
> + tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
> + tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx);
> + tcg_temp_free(addr_hi);
> } else {
> tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx);
> }
> return;
> case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv_i64 fp = tcg_temp_new_i64();
> - tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
> - gen_store_fpr64(fp, XREG(B11_8));
> - tcg_temp_free_i64(fp);
> + TCGv addr_hi = tcg_temp_new();
> + int fr = XREG(B11_8);
> + tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
> + tcg_temp_free(addr_hi);
> } else {
> tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
> }
> return;
> case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv_i64 fp = tcg_temp_new_i64();
> - tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
> - gen_store_fpr64(fp, XREG(B11_8));
> - tcg_temp_free_i64(fp);
> - tcg_gen_addi_i32(REG(B7_4),REG(B7_4), 8);
> + int fr = XREG(B11_8);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
> + tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], REG(B7_4), ctx->memidx);
> + tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
This is wrong, the address register should only be incremented after the
last load instruction, so that it has the correct value in case of
exception.
> } else {
> tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
> tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
> @@ -1023,16 +1027,13 @@ static void _decode_opc(DisasContext * ctx)
> return;
> case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv addr;
> - TCGv_i64 fp;
> - addr = tcg_temp_new();
> - tcg_gen_subi_i32(addr, REG(B11_8), 8);
> - fp = tcg_temp_new_i64();
> - gen_load_fpr64(fp, XREG(B7_4));
> - tcg_gen_qemu_st64(fp, addr, ctx->memidx);
> - tcg_temp_free_i64(fp);
> - tcg_temp_free(addr);
> + TCGv addr = tcg_temp_new_i32();
> + int fr = XREG(B7_4);
> + tcg_gen_subi_i32(addr, REG(B11_8), 4);
> tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
> + tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
> + tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx);
Same here.
> + tcg_temp_free(addr);
> } else {
> TCGv addr;
> addr = tcg_temp_new_i32();
> @@ -1047,10 +1048,10 @@ static void _decode_opc(DisasContext * ctx)
> TCGv addr = tcg_temp_new_i32();
> tcg_gen_add_i32(addr, REG(B7_4), REG(0));
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv_i64 fp = tcg_temp_new_i64();
> - tcg_gen_qemu_ld64(fp, addr, ctx->memidx);
> - gen_store_fpr64(fp, XREG(B11_8));
> - tcg_temp_free_i64(fp);
> + int fr = XREG(B11_8);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
> + tcg_gen_addi_i32(addr, addr, 4);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
> } else {
> tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx);
> }
> @@ -1062,10 +1063,10 @@ static void _decode_opc(DisasContext * ctx)
> TCGv addr = tcg_temp_new();
> tcg_gen_add_i32(addr, REG(B11_8), REG(0));
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv_i64 fp = tcg_temp_new_i64();
> - gen_load_fpr64(fp, XREG(B7_4));
> - tcg_gen_qemu_st64(fp, addr, ctx->memidx);
> - tcg_temp_free_i64(fp);
> + int fr = XREG(B7_4);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
> + tcg_gen_addi_i32(addr, addr, 4);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
> } else {
> tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
> }
Otherwise looks ok.
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 14+ messages in thread* [Qemu-devel] Re: [PATCH] target-sh4: fix 64-bit fmov to/from memory
2008-11-21 23:02 ` Aurelien Jarno
@ 2008-11-21 23:30 ` Måns Rullgård
2008-11-21 23:55 ` Aurelien Jarno
0 siblings, 1 reply; 14+ messages in thread
From: Måns Rullgård @ 2008-11-21 23:30 UTC (permalink / raw)
To: qemu-devel
Aurelien Jarno <aurelien@aurel32.net> writes:
> On Fri, Nov 21, 2008 at 10:23:54PM +0000, Mans Rullgard wrote:
>> When loading/storing a register pair, the even-numbered register
>> always maps to the low 32 bits of memory independently of target
>> endian configuration.
>>
>> Signed-off-by: Mans Rullgard <mans@mansr.com>
>> ---
>> target-sh4/translate.c | 61 ++++++++++++++++++++++++-----------------------
>> 1 files changed, 31 insertions(+), 30 deletions(-)
>>
>> diff --git a/target-sh4/translate.c b/target-sh4/translate.c
>> index 84a3f40..74894e9 100644
>> --- a/target-sh4/translate.c
>> +++ b/target-sh4/translate.c
>> @@ -991,31 +991,35 @@ static void _decode_opc(DisasContext * ctx)
>> return;
>> case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
>> if (ctx->fpscr & FPSCR_SZ) {
>> - TCGv_i64 fp = tcg_temp_new_i64();
>> - gen_load_fpr64(fp, XREG(B7_4));
>> - tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx);
>> - tcg_temp_free_i64(fp);
>> + TCGv addr_hi = tcg_temp_new();
>> + int fr = XREG(B7_4);
>> + tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
>> + tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
>> + tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx);
>> + tcg_temp_free(addr_hi);
>> } else {
>> tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx);
>> }
>> return;
>> case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
>> if (ctx->fpscr & FPSCR_SZ) {
>> - TCGv_i64 fp = tcg_temp_new_i64();
>> - tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
>> - gen_store_fpr64(fp, XREG(B11_8));
>> - tcg_temp_free_i64(fp);
>> + TCGv addr_hi = tcg_temp_new();
>> + int fr = XREG(B11_8);
>> + tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
>> + tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
>> + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
>> + tcg_temp_free(addr_hi);
>> } else {
>> tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
>> }
>> return;
>> case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
>> if (ctx->fpscr & FPSCR_SZ) {
>> - TCGv_i64 fp = tcg_temp_new_i64();
>> - tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
>> - gen_store_fpr64(fp, XREG(B11_8));
>> - tcg_temp_free_i64(fp);
>> - tcg_gen_addi_i32(REG(B7_4),REG(B7_4), 8);
>> + int fr = XREG(B11_8);
>> + tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
>> + tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
>> + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], REG(B7_4), ctx->memidx);
>> + tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
>
> This is wrong, the address register should only be incremented after the
> last load instruction, so that it has the correct value in case of
> exception.
You're quite right. In fact, shouldn't the 32-bit values be loaded
into a temporary locations (at least the first to be loaded) in case
the second load generates an exception? The manual doesn't seem to
allow a partial load in such a situation, so I'd assume it's not safe.
--
Måns Rullgård
mans@mansr.com
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [Qemu-devel] Re: [PATCH] target-sh4: fix 64-bit fmov to/from memory
2008-11-21 23:30 ` [Qemu-devel] " Måns Rullgård
@ 2008-11-21 23:55 ` Aurelien Jarno
2008-11-22 0:51 ` [Qemu-devel] " Mans Rullgard
0 siblings, 1 reply; 14+ messages in thread
From: Aurelien Jarno @ 2008-11-21 23:55 UTC (permalink / raw)
To: qemu-devel
On Fri, Nov 21, 2008 at 11:30:43PM +0000, Måns Rullgård wrote:
> Aurelien Jarno <aurelien@aurel32.net> writes:
>
> > On Fri, Nov 21, 2008 at 10:23:54PM +0000, Mans Rullgard wrote:
> >> When loading/storing a register pair, the even-numbered register
> >> always maps to the low 32 bits of memory independently of target
> >> endian configuration.
> >>
> >> Signed-off-by: Mans Rullgard <mans@mansr.com>
> >> ---
> >> target-sh4/translate.c | 61 ++++++++++++++++++++++++-----------------------
> >> 1 files changed, 31 insertions(+), 30 deletions(-)
> >>
> >> diff --git a/target-sh4/translate.c b/target-sh4/translate.c
> >> index 84a3f40..74894e9 100644
> >> --- a/target-sh4/translate.c
> >> +++ b/target-sh4/translate.c
> >> @@ -991,31 +991,35 @@ static void _decode_opc(DisasContext * ctx)
> >> return;
> >> case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
> >> if (ctx->fpscr & FPSCR_SZ) {
> >> - TCGv_i64 fp = tcg_temp_new_i64();
> >> - gen_load_fpr64(fp, XREG(B7_4));
> >> - tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx);
> >> - tcg_temp_free_i64(fp);
> >> + TCGv addr_hi = tcg_temp_new();
> >> + int fr = XREG(B7_4);
> >> + tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
> >> + tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
> >> + tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx);
> >> + tcg_temp_free(addr_hi);
> >> } else {
> >> tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx);
> >> }
> >> return;
> >> case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
> >> if (ctx->fpscr & FPSCR_SZ) {
> >> - TCGv_i64 fp = tcg_temp_new_i64();
> >> - tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
> >> - gen_store_fpr64(fp, XREG(B11_8));
> >> - tcg_temp_free_i64(fp);
> >> + TCGv addr_hi = tcg_temp_new();
> >> + int fr = XREG(B11_8);
> >> + tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
> >> + tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
> >> + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
> >> + tcg_temp_free(addr_hi);
> >> } else {
> >> tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
> >> }
> >> return;
> >> case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
> >> if (ctx->fpscr & FPSCR_SZ) {
> >> - TCGv_i64 fp = tcg_temp_new_i64();
> >> - tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
> >> - gen_store_fpr64(fp, XREG(B11_8));
> >> - tcg_temp_free_i64(fp);
> >> - tcg_gen_addi_i32(REG(B7_4),REG(B7_4), 8);
> >> + int fr = XREG(B11_8);
> >> + tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
> >> + tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
> >> + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], REG(B7_4), ctx->memidx);
> >> + tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
> >
> > This is wrong, the address register should only be incremented after the
> > last load instruction, so that it has the correct value in case of
> > exception.
>
> You're quite right. In fact, shouldn't the 32-bit values be loaded
> into a temporary locations (at least the first to be loaded) in case
> the second load generates an exception? The manual doesn't seem to
> allow a partial load in such a situation, so I'd assume it's not safe.
>
There is nothing in the manual, but on most CPUs the value in the
register is then defined as unpredictable. I don't think it is important
to preserve the register value at this point. Preserving the address
value is important so that the instruction could be re-executed after an
exception, like a TLB miss for example.
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 14+ messages in thread* [Qemu-devel] [PATCH] target-sh4: fix 64-bit fmov to/from memory
2008-11-21 23:55 ` Aurelien Jarno
@ 2008-11-22 0:51 ` Mans Rullgard
2008-11-22 10:09 ` Aurelien Jarno
0 siblings, 1 reply; 14+ messages in thread
From: Mans Rullgard @ 2008-11-22 0:51 UTC (permalink / raw)
To: qemu-devel
When loading/storing a register pair, the even-numbered register
always maps to the low 32 bits of memory independently of target
endian configuration.
Signed-off-by: Mans Rullgard <mans@mansr.com>
---
target-sh4/translate.c | 62 +++++++++++++++++++++++++----------------------
1 files changed, 33 insertions(+), 29 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 84a3f40..bbfd745 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -991,31 +991,37 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- gen_load_fpr64(fp, XREG(B7_4));
- tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx);
- tcg_temp_free_i64(fp);
+ TCGv addr_hi = tcg_temp_new();
+ int fr = XREG(B7_4);
+ tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
+ tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
+ tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx);
+ tcg_temp_free(addr_hi);
} else {
tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx);
}
return;
case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
- gen_store_fpr64(fp, XREG(B11_8));
- tcg_temp_free_i64(fp);
+ TCGv addr_hi = tcg_temp_new();
+ int fr = XREG(B11_8);
+ tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
+ tcg_temp_free(addr_hi);
} else {
tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
}
return;
case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
- gen_store_fpr64(fp, XREG(B11_8));
- tcg_temp_free_i64(fp);
- tcg_gen_addi_i32(REG(B7_4),REG(B7_4), 8);
+ TCGv addr_hi = tcg_temp_new();
+ int fr = XREG(B11_8);
+ tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
+ tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8);
+ tcg_temp_free(addr_hi);
} else {
tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
@@ -1023,16 +1029,14 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- TCGv addr;
- TCGv_i64 fp;
- addr = tcg_temp_new();
+ TCGv addr = tcg_temp_new_i32();
+ int fr = XREG(B7_4);
+ tcg_gen_subi_i32(addr, REG(B11_8), 4);
+ tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx);
tcg_gen_subi_i32(addr, REG(B11_8), 8);
- fp = tcg_temp_new_i64();
- gen_load_fpr64(fp, XREG(B7_4));
- tcg_gen_qemu_st64(fp, addr, ctx->memidx);
- tcg_temp_free_i64(fp);
+ tcg_gen_qemu_st32(cpu_fregs[fr ], addr, ctx->memidx);
+ tcg_gen_mov_i32(REG(B11_8), addr);
tcg_temp_free(addr);
- tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
} else {
TCGv addr;
addr = tcg_temp_new_i32();
@@ -1047,10 +1051,10 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new_i32();
tcg_gen_add_i32(addr, REG(B7_4), REG(0));
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(fp, addr, ctx->memidx);
- gen_store_fpr64(fp, XREG(B11_8));
- tcg_temp_free_i64(fp);
+ int fr = XREG(B11_8);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
+ tcg_gen_addi_i32(addr, addr, 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
} else {
tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx);
}
@@ -1062,10 +1066,10 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B11_8), REG(0));
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- gen_load_fpr64(fp, XREG(B7_4));
- tcg_gen_qemu_st64(fp, addr, ctx->memidx);
- tcg_temp_free_i64(fp);
+ int fr = XREG(B7_4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
+ tcg_gen_addi_i32(addr, addr, 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
} else {
tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
}
--
1.6.0.4
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [Qemu-devel] [PATCH] target-sh4: fix 64-bit fmov to/from memory
2008-11-22 0:51 ` [Qemu-devel] " Mans Rullgard
@ 2008-11-22 10:09 ` Aurelien Jarno
0 siblings, 0 replies; 14+ messages in thread
From: Aurelien Jarno @ 2008-11-22 10:09 UTC (permalink / raw)
To: qemu-devel
On Sat, Nov 22, 2008 at 12:51:39AM +0000, Mans Rullgard wrote:
> When loading/storing a register pair, the even-numbered register
> always maps to the low 32 bits of memory independently of target
> endian configuration.
Thanks, applied.
> Signed-off-by: Mans Rullgard <mans@mansr.com>
> ---
> target-sh4/translate.c | 62 +++++++++++++++++++++++++----------------------
> 1 files changed, 33 insertions(+), 29 deletions(-)
>
> diff --git a/target-sh4/translate.c b/target-sh4/translate.c
> index 84a3f40..bbfd745 100644
> --- a/target-sh4/translate.c
> +++ b/target-sh4/translate.c
> @@ -991,31 +991,37 @@ static void _decode_opc(DisasContext * ctx)
> return;
> case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv_i64 fp = tcg_temp_new_i64();
> - gen_load_fpr64(fp, XREG(B7_4));
> - tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx);
> - tcg_temp_free_i64(fp);
> + TCGv addr_hi = tcg_temp_new();
> + int fr = XREG(B7_4);
> + tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
> + tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
> + tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx);
> + tcg_temp_free(addr_hi);
> } else {
> tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx);
> }
> return;
> case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv_i64 fp = tcg_temp_new_i64();
> - tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
> - gen_store_fpr64(fp, XREG(B11_8));
> - tcg_temp_free_i64(fp);
> + TCGv addr_hi = tcg_temp_new();
> + int fr = XREG(B11_8);
> + tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
> + tcg_temp_free(addr_hi);
> } else {
> tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
> }
> return;
> case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv_i64 fp = tcg_temp_new_i64();
> - tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
> - gen_store_fpr64(fp, XREG(B11_8));
> - tcg_temp_free_i64(fp);
> - tcg_gen_addi_i32(REG(B7_4),REG(B7_4), 8);
> + TCGv addr_hi = tcg_temp_new();
> + int fr = XREG(B11_8);
> + tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
> + tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8);
> + tcg_temp_free(addr_hi);
> } else {
> tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
> tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
> @@ -1023,16 +1029,14 @@ static void _decode_opc(DisasContext * ctx)
> return;
> case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv addr;
> - TCGv_i64 fp;
> - addr = tcg_temp_new();
> + TCGv addr = tcg_temp_new_i32();
> + int fr = XREG(B7_4);
> + tcg_gen_subi_i32(addr, REG(B11_8), 4);
> + tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx);
> tcg_gen_subi_i32(addr, REG(B11_8), 8);
> - fp = tcg_temp_new_i64();
> - gen_load_fpr64(fp, XREG(B7_4));
> - tcg_gen_qemu_st64(fp, addr, ctx->memidx);
> - tcg_temp_free_i64(fp);
> + tcg_gen_qemu_st32(cpu_fregs[fr ], addr, ctx->memidx);
> + tcg_gen_mov_i32(REG(B11_8), addr);
> tcg_temp_free(addr);
> - tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
> } else {
> TCGv addr;
> addr = tcg_temp_new_i32();
> @@ -1047,10 +1051,10 @@ static void _decode_opc(DisasContext * ctx)
> TCGv addr = tcg_temp_new_i32();
> tcg_gen_add_i32(addr, REG(B7_4), REG(0));
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv_i64 fp = tcg_temp_new_i64();
> - tcg_gen_qemu_ld64(fp, addr, ctx->memidx);
> - gen_store_fpr64(fp, XREG(B11_8));
> - tcg_temp_free_i64(fp);
> + int fr = XREG(B11_8);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
> + tcg_gen_addi_i32(addr, addr, 4);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
> } else {
> tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx);
> }
> @@ -1062,10 +1066,10 @@ static void _decode_opc(DisasContext * ctx)
> TCGv addr = tcg_temp_new();
> tcg_gen_add_i32(addr, REG(B11_8), REG(0));
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv_i64 fp = tcg_temp_new_i64();
> - gen_load_fpr64(fp, XREG(B7_4));
> - tcg_gen_qemu_st64(fp, addr, ctx->memidx);
> - tcg_temp_free_i64(fp);
> + int fr = XREG(B7_4);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
> + tcg_gen_addi_i32(addr, addr, 4);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
> } else {
> tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
> }
> --
> 1.6.0.4
>
>
>
>
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Qemu-devel] Re: [PATCH 1/2] target-sh4: fix 64-bit fmov to/from memory
2008-11-21 21:46 ` Aurelien Jarno
2008-11-21 22:23 ` [Qemu-devel] [PATCH] " Mans Rullgard
@ 2008-11-21 22:25 ` Måns Rullgård
1 sibling, 0 replies; 14+ messages in thread
From: Måns Rullgård @ 2008-11-21 22:25 UTC (permalink / raw)
To: qemu-devel
Aurelien Jarno <aurelien@aurel32.net> writes:
> On Fri, Nov 21, 2008 at 09:24:03PM +0000, Måns Rullgård wrote:
>> Aurelien Jarno <aurelien@aurel32.net> writes:
>>
>> > On Fri, Nov 21, 2008 at 07:55:41PM +0000, Mans Rullgard wrote:
>> >> When loading/storing a register pair, the even-numbered register
>> >> always maps to the low 32 bits of memory independently of target
>> >> endian configuration.
>> >>
>> >> Signed-off-by: Mans Rullgard <mans@mansr.com>
>> >> ---
>> >> target-sh4/translate.c | 63 ++++++++++++++++++++++++-----------------------
>> >> 1 files changed, 32 insertions(+), 31 deletions(-)
>> >>
>> >> diff --git a/target-sh4/translate.c b/target-sh4/translate.c
>> >> index 84a3f40..2d6dfe6 100644
>> >> --- a/target-sh4/translate.c
>> >> +++ b/target-sh4/translate.c
>> >> @@ -991,31 +991,35 @@ static void _decode_opc(DisasContext * ctx)
>> >> return;
>> >> case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
>> >> if (ctx->fpscr & FPSCR_SZ) {
>> >> - TCGv_i64 fp = tcg_temp_new_i64();
>> >> - gen_load_fpr64(fp, XREG(B7_4));
>> >> - tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx);
>> >> - tcg_temp_free_i64(fp);
>> >> + TCGv addr_hi = tcg_temp_new();
>> >> + int fr = XREG(B7_4);
>> >> + tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
>> >> + tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
>> >> + tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx);
>> >> + tcg_temp_free(addr_hi);
>> >
>> > You are totally breaking the indendation. Care to resend this patch with
>> > a proper indentation?
>>
>> I was told to use spaces for indentation even if surrounding code uses
>> tabs. I'll be happy to convert it to tabs if that's what you want.
>
> The current file use tabs. While it is not consistent with other qemu
> files, I think mixed indentation is even worse.
I can agree with that. New patch sent.
--
Måns Rullgård
mans@mansr.com
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Qemu-devel] [PATCH 1/2] target-sh4: fix 64-bit fmov to/from memory
@ 2008-11-21 0:46 Mans Rullgard
0 siblings, 0 replies; 14+ messages in thread
From: Mans Rullgard @ 2008-11-21 0:46 UTC (permalink / raw)
To: qemu-devel
When loading/storing a register pair, the even-numbered register
always maps to the low 32 bits of memory independently of target
endian configuration.
Signed-off-by: Mans Rullgard <mans@mansr.com>
---
target-sh4/translate.c | 63 ++++++++++++++++++++++++-----------------------
1 files changed, 32 insertions(+), 31 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 84a3f40..5ce1a0d 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -991,31 +991,35 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- gen_load_fpr64(fp, XREG(B7_4));
- tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx);
- tcg_temp_free_i64(fp);
+ TCGv fr = XREG(B7_4);
+ TCGv addr_hi = tcg_temp_new();
+ tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
+ tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
+ tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx);
+ tcg_temp_free(addr_hi);
} else {
tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx);
}
return;
case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
- gen_store_fpr64(fp, XREG(B11_8));
- tcg_temp_free_i64(fp);
+ TCGv fr = XREG(B11_8);
+ TCGv addr_hi = tcg_temp_new();
+ tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
+ tcg_temp_free(addr_hi);
} else {
tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
}
return;
case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
- gen_store_fpr64(fp, XREG(B11_8));
- tcg_temp_free_i64(fp);
- tcg_gen_addi_i32(REG(B7_4),REG(B7_4), 8);
+ int fr = XREG(B11_8);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
+ tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], REG(B7_4), ctx->memidx);
+ tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
} else {
tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
@@ -1023,16 +1027,13 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- TCGv addr;
- TCGv_i64 fp;
- addr = tcg_temp_new();
- tcg_gen_subi_i32(addr, REG(B11_8), 8);
- fp = tcg_temp_new_i64();
- gen_load_fpr64(fp, XREG(B7_4));
- tcg_gen_qemu_st64(fp, addr, ctx->memidx);
- tcg_temp_free_i64(fp);
- tcg_temp_free(addr);
- tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
+ TCGv addr = tcg_temp_new_i32();
+ TCGv fr = XREG(B7_4);
+ tcg_gen_subi_i32(addr, REG(B11_8), 4);
+ tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
+ tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
+ tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx);
+ tcg_temp_free(addr);
} else {
TCGv addr;
addr = tcg_temp_new_i32();
@@ -1047,10 +1048,10 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new_i32();
tcg_gen_add_i32(addr, REG(B7_4), REG(0));
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(fp, addr, ctx->memidx);
- gen_store_fpr64(fp, XREG(B11_8));
- tcg_temp_free_i64(fp);
+ TCGv fr = XREG(B11_8);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
+ tcg_gen_add_i32(addr, addr, 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
} else {
tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx);
}
@@ -1062,10 +1063,10 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B11_8), REG(0));
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- gen_load_fpr64(fp, XREG(B7_4));
- tcg_gen_qemu_st64(fp, addr, ctx->memidx);
- tcg_temp_free_i64(fp);
+ TCGv fr = XREG(B7_4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
+ tcg_gen_add_i32(addr, addr, 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
} else {
tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
}
--
1.6.0.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
end of thread, other threads:[~2009-02-03 20:28 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2008-11-21 19:55 [Qemu-devel] [PATCH 1/2] target-sh4: fix 64-bit fmov to/from memory Mans Rullgard
2008-11-21 19:55 ` [Qemu-devel] [PATCH 2/2] target-sh4: implement ftrv instruction Mans Rullgard
2009-02-03 20:28 ` Aurelien Jarno
2008-11-21 20:38 ` [Qemu-devel] [PATCH 1/2] target-sh4: fix 64-bit fmov to/from memory Aurelien Jarno
2008-11-21 21:24 ` [Qemu-devel] " Måns Rullgård
2008-11-21 21:46 ` Aurelien Jarno
2008-11-21 22:23 ` [Qemu-devel] [PATCH] " Mans Rullgard
2008-11-21 23:02 ` Aurelien Jarno
2008-11-21 23:30 ` [Qemu-devel] " Måns Rullgård
2008-11-21 23:55 ` Aurelien Jarno
2008-11-22 0:51 ` [Qemu-devel] " Mans Rullgard
2008-11-22 10:09 ` Aurelien Jarno
2008-11-21 22:25 ` [Qemu-devel] Re: [PATCH 1/2] " Måns Rullgård
-- strict thread matches above, loose matches on Subject: below --
2008-11-21 0:46 [Qemu-devel] " Mans Rullgard
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