From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1L3c6T-0007b4-4d for qemu-devel@nongnu.org; Fri, 21 Nov 2008 14:55:45 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1L3c6R-0007ZB-Hh for qemu-devel@nongnu.org; Fri, 21 Nov 2008 14:55:44 -0500 Received: from [199.232.76.173] (port=52748 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1L3c6R-0007Z2-9S for qemu-devel@nongnu.org; Fri, 21 Nov 2008 14:55:43 -0500 Received: from agrajag.mansr.com ([78.86.181.102]:55492 helo=mail.mansr.com) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1L3c6Q-0005VM-O0 for qemu-devel@nongnu.org; Fri, 21 Nov 2008 14:55:43 -0500 Received: from thrashbarg.mansr.com (thrashbarg.mansr.com [78.86.181.100]) by mail.mansr.com (Postfix) with ESMTP id 146FC1C0094 for ; Fri, 21 Nov 2008 19:55:42 +0000 (GMT) From: Mans Rullgard Date: Fri, 21 Nov 2008 19:55:42 +0000 Message-Id: <1227297342-5285-2-git-send-email-mans@mansr.com> In-Reply-To: <1227297342-5285-1-git-send-email-mans@mansr.com> References: <1227297342-5285-1-git-send-email-mans@mansr.com> Subject: [Qemu-devel] [PATCH 2/2] target-sh4: implement ftrv instruction Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This partially implements the ftrv instruction. It gives correct results under normal conditions. FPU exceptions are not correctly generated. Signed-off-by: Mans Rullgard --- target-sh4/translate.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 files changed, 40 insertions(+), 0 deletions(-) diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 2d6dfe6..9c2da41 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -1694,6 +1694,46 @@ static void _decode_opc(DisasContext * ctx) tcg_temp_free_i64(fp); } return; + case 0xf0fd: /* ftrv XMTRX,FVn */ + if ((ctx->opcode & 0x300) != 0x100) + break; + if (!(ctx->fpscr & FPSCR_PR)) { + TCGv fv[4]; + TCGv fp; + int n = B11_8 & 0xc; + int i; + + /* + * NOTE: The values calculated here are likely to differ + * from hardware since the hardware sacrifices accuracy + * for speed in this instruction. + * + * FIXME: FPU exceptions are not correctly raised here. + */ + + fp = tcg_temp_new(); + + for (i = 0; i < 4; i++) { + fv[i] = tcg_temp_new(); + tcg_gen_mov_i32(fv[i], cpu_fregs[n+i]); + } + + for (i = 0; i < 4; i++) { + gen_helper_fmul_FT(cpu_fregs[n+i], cpu_fregs[16+i], fv[0]); + gen_helper_fmul_FT(fp, cpu_fregs[20+i], fv[1]); + gen_helper_fadd_FT(cpu_fregs[n+i], cpu_fregs[n+i], fp); + gen_helper_fmul_FT(fp, cpu_fregs[24+i], fv[2]); + gen_helper_fadd_FT(cpu_fregs[n+i], cpu_fregs[n+i], fp); + gen_helper_fmul_FT(fp, cpu_fregs[28+i], fv[3]); + gen_helper_fadd_FT(cpu_fregs[n+i], cpu_fregs[n+i], fp); + } + + for (i = 0; i < 4; i++) + tcg_temp_free(fv[i]); + tcg_temp_free(fp); + return; + } + break; } fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n", -- 1.6.0.4