* [Qemu-devel] [PATCH] ARM: fix smmul and smmla instructions
@ 2008-11-25 23:27 Mans Rullgard
2008-11-26 8:41 ` Laurent Desnogues
0 siblings, 1 reply; 2+ messages in thread
From: Mans Rullgard @ 2008-11-25 23:27 UTC (permalink / raw)
To: qemu-devel
This fixes the destination and accumulator registers for the smmul
and smmla instructions.
Signed-off-by: Mans Rullgard <mans@mansr.com>
---
target-arm/translate.c | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 305a438..49e48c5 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -6507,8 +6507,8 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
tcg_gen_shri_i64(tmp64, tmp64, 32);
tmp = new_tmp();
tcg_gen_trunc_i64_i32(tmp, tmp64);
- if (rn != 15) {
- tmp2 = load_reg(s, rn);
+ if (rd != 15) {
+ tmp2 = load_reg(s, rd);
if (insn & (1 << 6)) {
tcg_gen_sub_i32(tmp, tmp, tmp2);
} else {
@@ -6516,7 +6516,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
}
dead_tmp(tmp2);
}
- store_reg(s, rd, tmp);
+ store_reg(s, rn, tmp);
} else {
if (insn & (1 << 5))
gen_swap_half(tmp2);
--
1.6.0.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [Qemu-devel] [PATCH] ARM: fix smmul and smmla instructions
2008-11-25 23:27 [Qemu-devel] [PATCH] ARM: fix smmul and smmla instructions Mans Rullgard
@ 2008-11-26 8:41 ` Laurent Desnogues
0 siblings, 0 replies; 2+ messages in thread
From: Laurent Desnogues @ 2008-11-26 8:41 UTC (permalink / raw)
To: qemu-devel
On Wed, Nov 26, 2008 at 12:27 AM, Mans Rullgard <mans@mansr.com> wrote:
> This fixes the destination and accumulator registers for the smmul
> and smmla instructions.
This patch is correct.
Laurent
> Signed-off-by: Mans Rullgard <mans@mansr.com>
> ---
> target-arm/translate.c | 6 +++---
> 1 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 305a438..49e48c5 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -6507,8 +6507,8 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
> tcg_gen_shri_i64(tmp64, tmp64, 32);
> tmp = new_tmp();
> tcg_gen_trunc_i64_i32(tmp, tmp64);
> - if (rn != 15) {
> - tmp2 = load_reg(s, rn);
> + if (rd != 15) {
> + tmp2 = load_reg(s, rd);
> if (insn & (1 << 6)) {
> tcg_gen_sub_i32(tmp, tmp, tmp2);
> } else {
> @@ -6516,7 +6516,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
> }
> dead_tmp(tmp2);
> }
> - store_reg(s, rd, tmp);
> + store_reg(s, rn, tmp);
> } else {
> if (insn & (1 << 5))
> gen_swap_half(tmp2);
> --
> 1.6.0.4
>
>
>
>
^ permalink raw reply [flat|nested] 2+ messages in thread
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