From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1L57JJ-0007rW-DO for qemu-devel@nongnu.org; Tue, 25 Nov 2008 18:27:13 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1L57JI-0007qz-KW for qemu-devel@nongnu.org; Tue, 25 Nov 2008 18:27:13 -0500 Received: from [199.232.76.173] (port=49322 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1L57JI-0007qn-Es for qemu-devel@nongnu.org; Tue, 25 Nov 2008 18:27:12 -0500 Received: from agrajag.mansr.com ([78.86.181.102]:43109 helo=mail.mansr.com) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1L57JI-00077R-1T for qemu-devel@nongnu.org; Tue, 25 Nov 2008 18:27:12 -0500 Received: from thrashbarg.mansr.com (thrashbarg.mansr.com [78.86.181.100]) by mail.mansr.com (Postfix) with ESMTP id 641C01C0096 for ; Tue, 25 Nov 2008 23:27:11 +0000 (GMT) From: Mans Rullgard Date: Tue, 25 Nov 2008 23:27:11 +0000 Message-Id: <1227655631-7852-1-git-send-email-mans@mansr.com> Subject: [Qemu-devel] [PATCH] ARM: fix smmul and smmla instructions Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This fixes the destination and accumulator registers for the smmul and smmla instructions. Signed-off-by: Mans Rullgard --- target-arm/translate.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 305a438..49e48c5 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -6507,8 +6507,8 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) tcg_gen_shri_i64(tmp64, tmp64, 32); tmp = new_tmp(); tcg_gen_trunc_i64_i32(tmp, tmp64); - if (rn != 15) { - tmp2 = load_reg(s, rn); + if (rd != 15) { + tmp2 = load_reg(s, rd); if (insn & (1 << 6)) { tcg_gen_sub_i32(tmp, tmp, tmp2); } else { @@ -6516,7 +6516,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) } dead_tmp(tmp2); } - store_reg(s, rd, tmp); + store_reg(s, rn, tmp); } else { if (insn & (1 << 5)) gen_swap_half(tmp2); -- 1.6.0.4