From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1L5Pxp-00056s-91 for qemu-devel@nongnu.org; Wed, 26 Nov 2008 14:22:17 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1L5Pxo-00056T-EX for qemu-devel@nongnu.org; Wed, 26 Nov 2008 14:22:16 -0500 Received: from [199.232.76.173] (port=45610 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1L5Pxo-00056P-9j for qemu-devel@nongnu.org; Wed, 26 Nov 2008 14:22:16 -0500 Received: from e8.ny.us.ibm.com ([32.97.182.138]:58524) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1L5Pxn-0006KS-9a for qemu-devel@nongnu.org; Wed, 26 Nov 2008 14:22:15 -0500 Received: from d01relay02.pok.ibm.com (d01relay02.pok.ibm.com [9.56.227.234]) by e8.ny.us.ibm.com (8.13.1/8.13.1) with ESMTP id mAQJHqiX021547 for ; Wed, 26 Nov 2008 14:17:52 -0500 Received: from d01av01.pok.ibm.com (d01av01.pok.ibm.com [9.56.224.215]) by d01relay02.pok.ibm.com (8.13.8/8.13.8/NCO v9.1) with ESMTP id mAQJMDOA108718 for ; Wed, 26 Nov 2008 14:22:13 -0500 Received: from d01av01.pok.ibm.com (loopback [127.0.0.1]) by d01av01.pok.ibm.com (8.12.11.20060308/8.13.3) with ESMTP id mAQJMC7j002178 for ; Wed, 26 Nov 2008 14:22:12 -0500 From: Hollis Blanchard Date: Wed, 26 Nov 2008 13:22:12 -0600 Message-Id: <1227727332-17939-1-git-send-email-hollisb@us.ibm.com> Subject: [Qemu-devel] [PATCH] IBM PowerPC 4xx 32-bit PCI controller emulation Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Hollis Blanchard This PCI controller can be found on a number of 4xx SoCs, including the 440EP. Signed-off-by: Hollis Blanchard --- This isn't yet used by the ppc405 boards qemu emulates, but it could be if someone has a 405 firmware/kernel they're able to test with. This patch is required for the ppc440 KVM support I have queued up, and has been tested with that (big-endian host, big-endian guest). --- Makefile.target | 2 +- hw/ppc4xx.h | 7 + hw/ppc4xx_pci.c | 370 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 378 insertions(+), 1 deletions(-) create mode 100644 hw/ppc4xx_pci.c diff --git a/Makefile.target b/Makefile.target index 3cdf7db..b22c306 100644 --- a/Makefile.target +++ b/Makefile.target @@ -679,7 +679,7 @@ OBJS+= heathrow_pic.o grackle_pci.o ppc_oldworld.o # NewWorld PowerMac OBJS+= unin_pci.o ppc_chrp.o # PowerPC 4xx boards -OBJS+= pflash_cfi02.o ppc4xx_devs.o ppc405_uc.o ppc405_boards.o +OBJS+= pflash_cfi02.o ppc4xx_devs.o ppc4xx_pci.o ppc405_uc.o ppc405_boards.o endif ifeq ($(TARGET_BASE_ARCH), mips) OBJS+= mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o diff --git a/hw/ppc4xx.h b/hw/ppc4xx.h index df959f8..98de2d4 100644 --- a/hw/ppc4xx.h +++ b/hw/ppc4xx.h @@ -25,6 +25,7 @@ #if !defined(PPC_4XX_H) #define PPC_4XX_H +#include "pci.h" #include "ppc.h" /* PowerPC 4xx core initialization */ @@ -48,4 +49,10 @@ enum { qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs, uint32_t dcr_base, int has_ssr, int has_vr); +PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq *pic, + target_phys_addr_t config_space, + target_phys_addr_t int_ack, + target_phys_addr_t special_cycle, + target_phys_addr_t registers); + #endif /* !defined(PPC_4XX_H) */ diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c new file mode 100644 index 0000000..c9c832a --- /dev/null +++ b/hw/ppc4xx_pci.c @@ -0,0 +1,370 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + * Copyright IBM Corp. 2008 + * + * Authors: Hollis Blanchard + */ + +/* This file implements emulation of the 32-bit PCI controller found in some + * 440 SoCs, such as the 440EP. */ + +#include "hw.h" + +typedef target_phys_addr_t pci_addr_t; +#include "pci.h" +#include "pci_host.h" +#include "bswap.h" + +struct pci_master_map { + uint32_t la; + uint32_t ma; + uint32_t pcila; + uint32_t pciha; +}; + +struct pci_target_map { + uint32_t ms; + uint32_t la; + uint32_t bar; +}; + +#define PPC44x_PCI_NR_PMMS 3 +#define PPC44x_PCI_NR_PTMS 2 + +struct ppc4xx_pci_t { + target_phys_addr_t config_space; + target_phys_addr_t registers; + struct pci_master_map pmm[PPC44x_PCI_NR_PMMS]; + struct pci_target_map ptm[PPC44x_PCI_NR_PTMS]; + + unsigned int pmm_offset_flags; + qemu_irq *pic; + + PCIHostState pci_state; +}; +typedef struct ppc4xx_pci_t ppc4xx_pci_t; + +#define PCIC0_CFGADDR 0x0 +#define PCIC0_CFGDATA 0x4 + +/* PLB Memory Map (PMM) registers specify which PLB addresses are translated to + * PCI accesses. */ +#define PCIL0_PMM0LA 0x0 +#define PCIL0_PMM0MA 0x4 +#define PCIL0_PMM0PCILA 0x8 +#define PCIL0_PMM0PCIHA 0xc +#define PCIL0_PMM1LA 0x10 +#define PCIL0_PMM1MA 0x14 +#define PCIL0_PMM1PCILA 0x18 +#define PCIL0_PMM1PCIHA 0x1c +#define PCIL0_PMM2LA 0x20 +#define PCIL0_PMM2MA 0x24 +#define PCIL0_PMM2PCILA 0x28 +#define PCIL0_PMM2PCIHA 0x2c + +/* PCI Target Map (PTM) registers specify which PCI addresses are translated to + * PLB accesses. */ +#define PCIL0_PTM1MS 0x30 +#define PCIL0_PTM1LA 0x34 +#define PCIL0_PTM2MS 0x38 +#define PCIL0_PTM2LA 0x3c +#define PCI_REG_SIZE 0x40 + + +static uint32_t pci4xx_cfgaddr_readl(void *opaque, target_phys_addr_t addr) +{ + ppc4xx_pci_t *ppc4xx_pci = opaque; + + return ppc4xx_pci->pci_state.config_reg; +} + +static CPUReadMemoryFunc *pci4xx_cfgaddr_read[] = { + &pci4xx_cfgaddr_readl, + &pci4xx_cfgaddr_readl, + &pci4xx_cfgaddr_readl, +}; + +static void pci4xx_cfgaddr_writel(void *opaque, target_phys_addr_t addr, + uint32_t value) +{ + ppc4xx_pci_t *ppc4xx_pci = opaque; + +#ifdef TARGET_WORDS_BIGENDIAN + value = bswap32(value); +#endif + + ppc4xx_pci->pci_state.config_reg = value & ~0x3; +} + +static CPUWriteMemoryFunc *pci4xx_cfgaddr_write[] = { + &pci4xx_cfgaddr_writel, + &pci4xx_cfgaddr_writel, + &pci4xx_cfgaddr_writel, +}; + +static CPUReadMemoryFunc *pci4xx_cfgdata_read[] = { + &pci_host_data_readb, + &pci_host_data_readw, + &pci_host_data_readl, +}; + +static CPUWriteMemoryFunc *pci4xx_cfgdata_write[] = { + &pci_host_data_writeb, + &pci_host_data_writew, + &pci_host_data_writel, +}; + +static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t addr, + uint32_t value) +{ + struct ppc4xx_pci_t *pci = opaque; + unsigned long offset = addr - pci->registers; + +#ifdef TARGET_WORDS_BIGENDIAN + value = bswap32(value); +#endif + + /* We ignore all target attempts at PCI configuration, effectively + * assuming a bidirectional 1:1 mapping of PLB and PCI space. */ + + switch (offset) { + case PCIL0_PMM0LA: + pci->pmm[0].la = value; + break; + case PCIL0_PMM0MA: + pci->pmm[0].ma = value; + break; + case PCIL0_PMM0PCIHA: + pci->pmm[0].pciha = value; + break; + case PCIL0_PMM0PCILA: + pci->pmm[0].pcila = value; + break; + + case PCIL0_PMM1LA: + pci->pmm[1].la = value; + break; + case PCIL0_PMM1MA: + pci->pmm[1].ma = value; + break; + case PCIL0_PMM1PCIHA: + pci->pmm[1].pciha = value; + break; + case PCIL0_PMM1PCILA: + pci->pmm[1].pcila = value; + break; + + case PCIL0_PMM2LA: + pci->pmm[2].la = value; + break; + case PCIL0_PMM2MA: + pci->pmm[2].ma = value; + break; + case PCIL0_PMM2PCIHA: + pci->pmm[2].pciha = value; + break; + case PCIL0_PMM2PCILA: + pci->pmm[2].pcila = value; + break; + + case PCIL0_PTM1MS: + pci->ptm[0].ms = value; + break; + case PCIL0_PTM1LA: + pci->ptm[0].la = value; + break; + case PCIL0_PTM2MS: + pci->ptm[1].ms = value; + break; + case PCIL0_PTM2LA: + pci->ptm[1].la = value; + break; + + default: + printf(" write to unhandled PCI internal register 0x%lx\n", offset); + break; + } +} + +static uint32_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t addr) +{ + struct ppc4xx_pci_t *pci = opaque; + unsigned long offset = addr - pci->registers; + uint32_t value; + + switch (offset) { + case PCIL0_PMM0LA: + value = pci->pmm[0].la; + break; + case PCIL0_PMM0MA: + value = pci->pmm[0].ma; + break; + case PCIL0_PMM0PCIHA: + value = pci->pmm[0].pciha; + break; + case PCIL0_PMM0PCILA: + value = pci->pmm[0].pcila; + break; + + case PCIL0_PMM1LA: + value = pci->pmm[1].la; + break; + case PCIL0_PMM1MA: + value = pci->pmm[1].ma; + break; + case PCIL0_PMM1PCIHA: + value = pci->pmm[1].pciha; + break; + case PCIL0_PMM1PCILA: + value = pci->pmm[1].pcila; + break; + + case PCIL0_PMM2LA: + value = pci->pmm[2].la; + break; + case PCIL0_PMM2MA: + value = pci->pmm[2].ma; + break; + case PCIL0_PMM2PCIHA: + value = pci->pmm[2].pciha; + break; + case PCIL0_PMM2PCILA: + value = pci->pmm[2].pcila; + break; + + case PCIL0_PTM1MS: + value = pci->ptm[0].ms; + break; + case PCIL0_PTM1LA: + value = pci->ptm[0].la; + break; + case PCIL0_PTM2MS: + value = pci->ptm[1].ms; + break; + case PCIL0_PTM2LA: + value = pci->ptm[1].la; + break; + + default: + printf(" read from invalid PCI internal register 0x%lx\n", offset); + value = 0; + } + +#ifdef TARGET_WORDS_BIGENDIAN + value = bswap32(value); +#endif + + return value; +} + +static CPUReadMemoryFunc *pci_reg_read[] = { + &ppc4xx_pci_reg_read4, + &ppc4xx_pci_reg_read4, + &ppc4xx_pci_reg_read4, +}; + +static CPUWriteMemoryFunc *pci_reg_write[] = { + &ppc4xx_pci_reg_write4, + &ppc4xx_pci_reg_write4, + &ppc4xx_pci_reg_write4, +}; + +static int bamboo_pci_map_irq(PCIDevice *pci_dev, int irq_num) +{ + int slot = pci_dev->devfn >> 3; + +#if 0 + printf("### %s: devfn %x irq %d -> %d\n", __func__, + pci_dev->devfn, irq_num, slot+1); +#endif + + /* All pins from each slot are tied to a single board IRQ (2-5) */ + /* XXX Needs some abstracting for boards other than Bamboo. */ + return slot + 1; +} + +static void bamboo_pci_set_irq(qemu_irq *pic, int irq_num, int level) +{ +#if 0 + printf("### %s: PCI irq %d, UIC irq %d\n", __func__, irq_num, 30 - irq_num); +#endif + + /* Board IRQs 2-5 are connected to UIC IRQs 28-25 */ + /* XXX Needs some abstracting for boards other than Bamboo. */ + qemu_set_irq(pic[30-irq_num], level); +} + +/* XXX Interrupt acknowledge cycles not supported. */ +PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq *pic, + target_phys_addr_t config_space, + target_phys_addr_t int_ack, + target_phys_addr_t special_cycle, + target_phys_addr_t registers) +{ + ppc4xx_pci_t *controller; + PCIDevice *d; + int index; + + controller = qemu_mallocz(sizeof(ppc4xx_pci_t)); + if (!controller) + return NULL; + + controller->config_space = config_space; + controller->registers = registers; + controller->pic = pic; + + controller->pci_state.bus = pci_register_bus(bamboo_pci_set_irq, + bamboo_pci_map_irq, + pic, 0, 4); + + d = pci_register_device(controller->pci_state.bus, "host bridge", + sizeof(PCIDevice), 0, NULL, NULL); + d->config[0x00] = 0x14; // vendor_id + d->config[0x01] = 0x10; + d->config[0x02] = 0x7f; // device_id + d->config[0x03] = 0x02; + d->config[0x0a] = 0x80; // class_sub = other bridge type + d->config[0x0b] = 0x06; // class_base = PCI_bridge + + /* CFGADDR */ + index = cpu_register_io_memory(0, pci4xx_cfgaddr_read, + pci4xx_cfgaddr_write, controller); + if (index < 0) + goto free; + cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index); + + /* CFGDATA */ + index = cpu_register_io_memory(0, pci4xx_cfgdata_read, + pci4xx_cfgdata_write, + &controller->pci_state); + if (index < 0) + goto free; + cpu_register_physical_memory(config_space + PCIC0_CFGDATA, 4, index); + + /* Internal registers */ + index = cpu_register_io_memory(0, pci_reg_read, pci_reg_write, controller); + if (index < 0) + goto free; + cpu_register_physical_memory(registers, PCI_REG_SIZE, index); + + /* XXX register_savevm() */ + + return controller->pci_state.bus; + +free: + printf("%s error\n", __func__); + qemu_free(controller); + return NULL; +} -- 1.5.6.5