[Qemu-devel] [PATCH 0/2] ARMv6 fixes

[Qemu-devel] [PATCH 0/2] ARMv6 fixes

[Mans Rullgard]

Resending two small patches fixing a few ARMv6 instructions.

Mans Rullgard (2):
  ARM: fix usad8 and usada8 instructions
  ARM: fix smmul and smmla instructions

 target-arm/translate.c |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

[Qemu-devel] [PATCH 1/2] ARM: fix usad8 and usada8 instructions

[Mans Rullgard]

This fixes the destination and accumulator registers for the usad8
and usada8 instructions.

Signed-off-by: Mans Rullgard <mans@mansr.com>
---
 target-arm/translate.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index f984de7..424a4a6 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -6581,12 +6581,12 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
                         tmp2 = load_reg(s, rs);
                         gen_helper_usad8(tmp, tmp, tmp2);
                         dead_tmp(tmp2);
-                        if (rn != 15) {
-                            tmp2 = load_reg(s, rn);
+                        if (rd != 15) {
+                            tmp2 = load_reg(s, rd);
                             tcg_gen_add_i32(tmp, tmp, tmp2);
                             dead_tmp(tmp2);
                         }
-                        store_reg(s, rd, tmp);
+                        store_reg(s, rn, tmp);
                         break;
                     case 0x20: case 0x24: case 0x28: case 0x2c:
                         /* Bitfield insert/clear.  */
-- 
1.6.0.4

[Qemu-devel] [PATCH 2/2] ARM: fix smmul and smmla instructions

[Mans Rullgard]

This fixes the destination and accumulator registers for the smmul
and smmla instructions.

Signed-off-by: Mans Rullgard <mans@mansr.com>
---
 target-arm/translate.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 424a4a6..d8f4d03 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -6532,8 +6532,8 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
                         tcg_gen_shri_i64(tmp64, tmp64, 32);
                         tmp = new_tmp();
                         tcg_gen_trunc_i64_i32(tmp, tmp64);
-                        if (rn != 15) {
-                            tmp2 = load_reg(s, rn);
+                        if (rd != 15) {
+                            tmp2 = load_reg(s, rd);
                             if (insn & (1 << 6)) {
                                 tcg_gen_sub_i32(tmp, tmp, tmp2);
                             } else {
@@ -6541,7 +6541,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
                             }
                             dead_tmp(tmp2);
                         }
-                        store_reg(s, rd, tmp);
+                        store_reg(s, rn, tmp);
                     } else {
                         if (insn & (1 << 5))
                             gen_swap_half(tmp2);
-- 
1.6.0.4