From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1L7FgJ-0001Cl-3G for qemu-devel@nongnu.org; Mon, 01 Dec 2008 15:47:47 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1L7FgF-0001Bp-Ps for qemu-devel@nongnu.org; Mon, 01 Dec 2008 15:47:45 -0500 Received: from [199.232.76.173] (port=49754 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1L7FgF-0001Bf-GU for qemu-devel@nongnu.org; Mon, 01 Dec 2008 15:47:43 -0500 Received: from agrajag.mansr.com ([78.86.181.102]:59783 helo=mail.mansr.com) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1L7FgD-0005dP-SD for qemu-devel@nongnu.org; Mon, 01 Dec 2008 15:47:43 -0500 Received: from thrashbarg.mansr.com (thrashbarg.mansr.com [78.86.181.100]) by mail.mansr.com (Postfix) with ESMTP id A902E1C008F for ; Mon, 1 Dec 2008 20:47:36 +0000 (GMT) From: Mans Rullgard Date: Mon, 1 Dec 2008 20:47:36 +0000 Message-Id: <1228164456-4379-3-git-send-email-mans@mansr.com> In-Reply-To: <1228164456-4379-1-git-send-email-mans@mansr.com> References: <1228164456-4379-1-git-send-email-mans@mansr.com> Subject: [Qemu-devel] [PATCH 2/2] ARM: fix smmul and smmla instructions Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This fixes the destination and accumulator registers for the smmul and smmla instructions. Signed-off-by: Mans Rullgard --- target-arm/translate.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 424a4a6..d8f4d03 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -6532,8 +6532,8 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) tcg_gen_shri_i64(tmp64, tmp64, 32); tmp = new_tmp(); tcg_gen_trunc_i64_i32(tmp, tmp64); - if (rn != 15) { - tmp2 = load_reg(s, rn); + if (rd != 15) { + tmp2 = load_reg(s, rd); if (insn & (1 << 6)) { tcg_gen_sub_i32(tmp, tmp, tmp2); } else { @@ -6541,7 +6541,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) } dead_tmp(tmp2); } - store_reg(s, rd, tmp); + store_reg(s, rn, tmp); } else { if (insn & (1 << 5)) gen_swap_half(tmp2); -- 1.6.0.4