From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LC3Pe-0008Ir-Rw for qemu-devel@nongnu.org; Sun, 14 Dec 2008 21:42:27 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LC3Pa-0008GB-Fk for qemu-devel@nongnu.org; Sun, 14 Dec 2008 21:42:26 -0500 Received: from [199.232.76.173] (port=45205 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LC3Pa-0008Fr-5v for qemu-devel@nongnu.org; Sun, 14 Dec 2008 21:42:22 -0500 Received: from mx20.gnu.org ([199.232.41.8]:31627) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LC3PZ-0002hz-Eu for qemu-devel@nongnu.org; Sun, 14 Dec 2008 21:42:21 -0500 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LC3PR-0002tW-O8 for qemu-devel@nongnu.org; Sun, 14 Dec 2008 21:42:14 -0500 From: Nathan Froyd Date: Sun, 14 Dec 2008 18:14:42 -0800 Message-Id: <1229307315-16807-10-git-send-email-froydnj@codesourcery.com> In-Reply-To: <1229307315-16807-1-git-send-email-froydnj@codesourcery.com> References: <1229307315-16807-1-git-send-email-froydnj@codesourcery.com> Subject: [Qemu-devel] [PATCH 09/42] target-ppc: add GEN_VXRFORM{, 1} macros for subsequent instructions. Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Signed-off-by: Nathan Froyd --- target-ppc/translate.c | 27 +++++++++++++++++++++++++++ 1 files changed, 27 insertions(+), 0 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 0266942..53cff59 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -6176,6 +6176,33 @@ GEN_VXFORM(vavgsb, 1282); GEN_VXFORM(vavgsh, 1346); GEN_VXFORM(vavgsw, 1410); +#define GEN_VXRFORM1(opname, name, str, xo, rc) \ + GEN_HANDLER2(name, str, 0x4, (xo >> 1) & 0x1f, ((xo >> 6) & 0x1f) | (rc << 4), 0x00000000, PPC_ALTIVEC) \ + { \ + TCGv_ptr ra, rb, rd; \ + TCGv_i32 result; \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + ra = gen_avr_ptr(rA(ctx->opcode)); \ + rb = gen_avr_ptr(rB(ctx->opcode)); \ + rd = gen_avr_ptr(rD(ctx->opcode)); \ + result = tcg_temp_new_i32(); \ + gen_helper_##opname (result, rd, ra, rb); \ + if (rc) { \ + tcg_gen_mov_i32(cpu_crf[6], result); \ + } \ + tcg_temp_free(ra); \ + tcg_temp_free(rb); \ + tcg_temp_free(rd); \ + tcg_temp_free_i32(result); \ + } + +#define GEN_VXRFORM(name, xo) \ + GEN_VXRFORM1(name, name, #name, xo, 0) \ + GEN_VXRFORM1(name, name##_, #name ".", xo, 1) + /*** SPE extension ***/ /* Register moves */ -- 1.6.0.5