From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LC2zX-0002Ra-Lw for qemu-devel@nongnu.org; Sun, 14 Dec 2008 21:15:27 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LC2zW-0002QW-G0 for qemu-devel@nongnu.org; Sun, 14 Dec 2008 21:15:27 -0500 Received: from [199.232.76.173] (port=40884 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LC2zV-0002QB-Vz for qemu-devel@nongnu.org; Sun, 14 Dec 2008 21:15:26 -0500 Received: from mx20.gnu.org ([199.232.41.8]:31124) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LC2zV-0000bm-NK for qemu-devel@nongnu.org; Sun, 14 Dec 2008 21:15:25 -0500 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LC2zU-0002Db-Th for qemu-devel@nongnu.org; Sun, 14 Dec 2008 21:15:25 -0500 From: Nathan Froyd Date: Sun, 14 Dec 2008 18:14:34 -0800 Message-Id: <1229307315-16807-2-git-send-email-froydnj@codesourcery.com> In-Reply-To: <1229307315-16807-1-git-send-email-froydnj@codesourcery.com> References: <1229307315-16807-1-git-send-email-froydnj@codesourcery.com> Subject: [Qemu-devel] [PATCH 01/42] target-ppc: add Altivec logical operations. Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Signed-off-by: Nathan Froyd --- target-ppc/translate.c | 18 ++++++++++++++++++ 1 files changed, 18 insertions(+), 0 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 4c4f9ef..70047c7 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -6109,6 +6109,24 @@ GEN_VR_STX(svx, 0x07, 0x07); /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ GEN_VR_STX(svxl, 0x07, 0x0F); +/* Logical operations */ +#define GEN_VX_LOGICAL(name, tcg_op, xo) \ +GEN_HANDLER(name, 0x04, (xo >> 1) & 0x1f, (xo >> 6) & 0x1f, 0x00000000, PPC_ALTIVEC) \ +{ \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \ + tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \ +} + +GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 1028); +GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 1092); +GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 1156); +GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 1220); +GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 1284); + /*** SPE extension ***/ /* Register moves */ -- 1.6.0.5