[Qemu-devel] [PATCH] target-ppc: add Altivec instructions, corrections

[Qemu-devel] [PATCH] target-ppc: add Altivec instructions, corrections

[Nathan Froyd]

[Apologies for sending this as a separate, smaller series; I lost the
original thread, or else I'd reply to those.]

Actual testing against Altivec hardware revealed a few typos and thinkos
in my Altivec patch series.  This series can be applied at the
appropriate places in the original series and should be considered as
superseding the corresponding patches.

The only thing that does work is m{f,t}vscr; I've verified that
instructions that set bits in vscr operate properly, but at least mfvscr
doesn't actually update the register with the contents of vscr.  I'm at
a loss to figure out why.  Advice welcome...

-Nathan

[Qemu-devel] [PATCH 13/42] target-ppc: add vmul{e, o}{s, u}{b, h} instructions.

[Nathan Froyd]

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
 target-ppc/helper.h    |    8 ++++++++
 target-ppc/op_helper.c |   22 ++++++++++++++++++++++
 target-ppc/translate.c |    8 ++++++++
 3 files changed, 38 insertions(+), 0 deletions(-)

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 5a05157..6b74c3d 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -138,6 +138,14 @@ DEF_HELPER_3(vcmpgtuw, i32, avr, avr, avr)
 DEF_HELPER_3(vcmpgtsb, i32, avr, avr, avr)
 DEF_HELPER_3(vcmpgtsh, i32, avr, avr, avr)
 DEF_HELPER_3(vcmpgtsw, i32, avr, avr, avr)
+DEF_HELPER_3(vmulesb, void, avr, avr, avr)
+DEF_HELPER_3(vmulesh, void, avr, avr, avr)
+DEF_HELPER_3(vmuleub, void, avr, avr, avr)
+DEF_HELPER_3(vmuleuh, void, avr, avr, avr)
+DEF_HELPER_3(vmulosb, void, avr, avr, avr)
+DEF_HELPER_3(vmulosh, void, avr, avr, avr)
+DEF_HELPER_3(vmuloub, void, avr, avr, avr)
+DEF_HELPER_3(vmulouh, void, avr, avr, avr)
 
 DEF_HELPER_1(efscfsi, i32, i32)
 DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 886c1fa..33b018b 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2157,6 +2157,28 @@ VMRG(w, u32)
 #undef MRGHI
 #undef MRGLO
 
+#define VMUL_DO(name, mul_element, prod_element, evenp)                 \
+    void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)      \
+    {                                                                   \
+        int i;                                                          \
+        VECTOR_FOR_INORDER_I(i, prod_element) {                         \
+            if (evenp) {                                                \
+                r->prod_element[i] = a->mul_element[i*2+HI_IDX] * b->mul_element[i*2+HI_IDX]; \
+            } else {                                                    \
+                r->prod_element[i] = a->mul_element[i*2+LO_IDX] * b->mul_element[i*2+LO_IDX]; \
+            }                                                           \
+        }                                                               \
+    }
+#define VMUL(suffix, mul_element, prod_element) \
+  VMUL_DO(mule##suffix, mul_element, prod_element, 1) \
+  VMUL_DO(mulo##suffix, mul_element, prod_element, 0)
+VMUL(sb, s8, s16)
+VMUL(sh, s16, s32)
+VMUL(ub, u8, u16)
+VMUL(uh, u16, u32)
+#undef VMUL_DO
+#undef VMUL
+
 #undef VECTOR_FOR
 #undef VECTOR_FOR_I
 #undef VECTOR_FOR_INORDER_I
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 5b4c5cd..2d4ffbb 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6181,6 +6181,14 @@ GEN_VXFORM(vmrghw, 140);
 GEN_VXFORM(vmrglb, 268);
 GEN_VXFORM(vmrglh, 332);
 GEN_VXFORM(vmrglw, 396);
+GEN_VXFORM(vmuloub, 8);
+GEN_VXFORM(vmulouh, 72);
+GEN_VXFORM(vmulosb, 264);
+GEN_VXFORM(vmulosh, 328);
+GEN_VXFORM(vmuleub, 520);
+GEN_VXFORM(vmuleuh, 584);
+GEN_VXFORM(vmulesb, 776);
+GEN_VXFORM(vmulesh, 840);
 
 #define GEN_VXRFORM1(opname, name, str, xo, rc)                         \
     GEN_HANDLER2(name, str, 0x4, (xo >> 1) & 0x1f, ((xo >> 6) & 0x1f) | (rc << 4), 0x00000000, PPC_ALTIVEC) \
-- 
1.6.0.5

Re: [Qemu-devel] [PATCH 13/42] target-ppc: add vmul{e, o}{s, u}{b, h} instructions.

[Andreas Färber]

Am 15.12.2008 um 23:15 schrieb Nathan Froyd:

>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---

Since this looks like a resubmission, please include a short change log.

Andreas

Re: [Qemu-devel] [PATCH 13/42] target-ppc: add vmul{e, o}{s, u}{b, h} instructions.

[Nathan Froyd]

On Tue, Dec 16, 2008 at 12:01:41AM +0100, Andreas Färber wrote:
> Since this looks like a resubmission, please include a short change log.

Fix thinko and use a->mul_element instead of b->mul_element in the evenp
case in VMUL_DO.

-Nathan

[Qemu-devel] [PATCH 19/42] target-ppc: add m{f, t}vscr instructions.

[Nathan Froyd]

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
 target-ppc/translate.c |   37 +++++++++++++++++++++++++++++++++++++
 1 files changed, 37 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 791f76b..e72ff33 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6148,6 +6148,43 @@ GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC)
     tcg_temp_free(rd);
 }
 
+static always_inline uint32_t gen_vscr_offset (int r)
+{
+#if defined(WORDS_BIGENDIAN)
+    return offsetof(CPUPPCState, avr[r].u32[3]);
+#else
+    return offsetof(CPUPPCState, avr[r].u32[0]);
+#endif
+}
+
+GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC)
+{
+    TCGv_i32 t;
+    if (unlikely(!ctx->altivec_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_VPU);
+        return;
+    }
+    tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
+    tcg_gen_movi_i64(cpu_avrl[rD(ctx->opcode)], 0);
+    t = tcg_temp_new_i32();
+    tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr));
+    tcg_gen_st_i32(t, cpu_env, gen_vscr_offset(rD(ctx->opcode)));
+    tcg_temp_free_i32(t);
+}
+
+GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC)
+{
+    TCGv_i32 t;
+    if (unlikely(!ctx->altivec_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_VPU);
+        return;
+    }
+    t = tcg_temp_new_i32();
+    tcg_gen_ld_i32(t, cpu_env, gen_vscr_offset(rB(ctx->opcode)));
+    tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, vscr));
+    tcg_temp_free(t);
+}
+
 /* Logical operations */
 #define GEN_VX_LOGICAL(name, tcg_op, xo)                                \
 GEN_HANDLER(name, 0x04, (xo >> 1) & 0x1f, (xo >> 6) & 0x1f, 0x00000000, PPC_ALTIVEC) \
-- 
1.6.0.5

Re: [Qemu-devel] [PATCH 19/42] target-ppc: add m{f, t}vscr instructions.

[Nathan Froyd]

On Mon, Dec 15, 2008 at 02:15:34PM -0800, Nathan Froyd wrote:
>  target-ppc/translate.c |   37 +++++++++++++++++++++++++++++++++++++
>  1 files changed, 37 insertions(+), 0 deletions(-)

Change from previous version:

Don't use cpu_vscr; instead, work with vscr directly from CPUState.
Also load/store vscr into the appropriate vector member, rather than
using bogus mov instructions.

-Nathan

[Qemu-devel] [PATCH 22/42] target-ppc: add vs{l,r} instructions.

[Nathan Froyd]

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
 target-ppc/helper.h    |    2 ++
 target-ppc/op_helper.c |   35 +++++++++++++++++++++++++++++++++++
 target-ppc/translate.c |    2 ++
 3 files changed, 39 insertions(+), 0 deletions(-)

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index cf2a655..5f94e9f 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -176,6 +176,8 @@ DEF_HELPER_3(vsubuws, void, avr, avr, avr)
 DEF_HELPER_3(vrlb, void, avr, avr, avr)
 DEF_HELPER_3(vrlh, void, avr, avr, avr)
 DEF_HELPER_3(vrlw, void, avr, avr, avr)
+DEF_HELPER_3(vsl, void, avr, avr, avr)
+DEF_HELPER_3(vsr, void, avr, avr, avr)
 
 DEF_HELPER_1(efscfsi, i32, i32)
 DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 6c744c5..a55450b 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2264,6 +2264,41 @@ VROTATE(h, u16)
 VROTATE(w, u32)
 #undef VROTATE
 
+#if defined(WORDS_BIGENDIAN)
+#define LEFT 0
+#define RIGHT 1
+#else
+#define LEFT 1
+#define RIGHT 0
+#endif
+#define VSHIFT(suffix, leftp)                                           \
+    void helper_vs##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)   \
+    {                                                                   \
+        int shift = b->u8[LO_IDX*0x15] & 0x7;                           \
+        int doit = 1;                                                   \
+        VECTOR_FOR (u8) {                                               \
+            doit = doit && ((b->u8[i] & 0x7) == shift);                 \
+        }                                                               \
+        if (doit) {                                                     \
+            if (shift == 0) {                                           \
+                *r = *a;                                                \
+            } else if (leftp) {                                         \
+                uint64_t carry = a->u64[LO_IDX] >> (64 - shift);        \
+                r->u64[HI_IDX] = (a->u64[HI_IDX] << shift) | carry;     \
+                r->u64[LO_IDX] = a->u64[LO_IDX] << shift;               \
+            } else {                                                    \
+                uint64_t carry = a->u64[HI_IDX] << (64 - shift);        \
+                r->u64[LO_IDX] = (a->u64[LO_IDX] >> shift) | carry;     \
+                r->u64[HI_IDX] = a->u64[HI_IDX] >> shift;               \
+            }                                                           \
+        }                                                               \
+    }
+VSHIFT(l, LEFT)
+VSHIFT(r, RIGHT)
+#undef VSHIFT
+#undef LEFT
+#undef RIGHT
+
 #define VSL(suffix, element)                                            \
     void helper_vsl##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)  \
     {                                                                   \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 7c527b2..45657d2 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6286,6 +6286,8 @@ GEN_VXFORM(vsubsws, 1920);
 GEN_VXFORM(vrlb, 4);
 GEN_VXFORM(vrlh, 68);
 GEN_VXFORM(vrlw, 132);
+GEN_VXFORM(vsl, 452);
+GEN_VXFORM(vsr, 708);
 
 #define GEN_VXRFORM1(opname, name, str, xo, rc)                         \
     GEN_HANDLER2(name, str, 0x4, (xo >> 1) & 0x1f, ((xo >> 6) & 0x1f) | (rc << 4), 0x00000000, PPC_ALTIVEC) \
-- 
1.6.0.5

Re: [Qemu-devel] [PATCH 22/42] target-ppc: add vs{l,r} instructions.

[Nathan Froyd]

On Mon, Dec 15, 2008 at 02:15:35PM -0800, Nathan Froyd wrote:
>  target-ppc/helper.h    |    2 ++
>  target-ppc/op_helper.c |   35 +++++++++++++++++++++++++++++++++++
>  target-ppc/translate.c |    2 ++
>  3 files changed, 39 insertions(+), 0 deletions(-)

Change from previous version:

Fix bug in helper_vs{l,r}: we don't want to left- or right-shift R into
itself, but shift A and then store than into R.

-Nathan

[Qemu-devel] [PATCH] target-ppc: add Altivec instructions, patch-bomb version

[Nathan Froyd]

[Thiemo Seufer asked for a patch-bomb so people can conveniently comment
on things and so the mail archive has a record of Signed-off-by.]

This patch series adds support for integer Altivec instructions to QEMU,
including element-wise loads and stores.  It's a long patch series,
since each instruction "family" (element-wise loads/stores, modulo
arithmetic instructions, saturating arithmetic instructions, etc.) is
separated out into its own patch.  Hopefully since the individual
patches are so short, they will be more-or-less self-explanatory: the
explanation for the patches is generally fairly short, on the order of a
single line.

The patch series is slightly cleaned up from the one I originally
posted: there were a few problems with my tcg usage, and I didn't
faithfully use some convenience functions.

Why only the integer instructions?  I originally wrote support for the
whole instructions set, but I did it in the days of dyngen.  So a
straight forward-port was out of the question.  The original patch
sloppily used native floats everywhere, rather than the float32
abstraction.  It also used C99 math functions to implement some of the
more exotic Altivec instructions.  Both of these decisions mean that
some care has to be taken in porting the floating-point instructions.

I figured it'd be better to push out the integer instructions now and
the floating-point instructions later, rather than waiting for some
unspecified time for full support.

-Nathan

[Qemu-devel] [PATCH 13/42] target-ppc: add vmul{e, o}{s, u}{b, h} instructions.

[Nathan Froyd]

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
 target-ppc/helper.h    |    8 ++++++++
 target-ppc/op_helper.c |   22 ++++++++++++++++++++++
 target-ppc/translate.c |    8 ++++++++
 3 files changed, 38 insertions(+), 0 deletions(-)

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 5a05157..6b74c3d 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -138,6 +138,14 @@ DEF_HELPER_3(vcmpgtuw, i32, avr, avr, avr)
 DEF_HELPER_3(vcmpgtsb, i32, avr, avr, avr)
 DEF_HELPER_3(vcmpgtsh, i32, avr, avr, avr)
 DEF_HELPER_3(vcmpgtsw, i32, avr, avr, avr)
+DEF_HELPER_3(vmulesb, void, avr, avr, avr)
+DEF_HELPER_3(vmulesh, void, avr, avr, avr)
+DEF_HELPER_3(vmuleub, void, avr, avr, avr)
+DEF_HELPER_3(vmuleuh, void, avr, avr, avr)
+DEF_HELPER_3(vmulosb, void, avr, avr, avr)
+DEF_HELPER_3(vmulosh, void, avr, avr, avr)
+DEF_HELPER_3(vmuloub, void, avr, avr, avr)
+DEF_HELPER_3(vmulouh, void, avr, avr, avr)
 
 DEF_HELPER_1(efscfsi, i32, i32)
 DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 886c1fa..252fa4f 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2157,6 +2157,28 @@ VMRG(w, u32)
 #undef MRGHI
 #undef MRGLO
 
+#define VMUL_DO(name, mul_element, prod_element, evenp)                 \
+    void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)      \
+    {                                                                   \
+        int i;                                                          \
+        VECTOR_FOR_INORDER_I(i, prod_element) {                         \
+            if (evenp) {                                                \
+                r->prod_element[i] = b->mul_element[i*2+HI_IDX] * b->mul_element[i*2+HI_IDX]; \
+            } else {                                                    \
+                r->prod_element[i] = a->mul_element[i*2+LO_IDX] * b->mul_element[i*2+LO_IDX]; \
+            }                                                           \
+        }                                                               \
+    }
+#define VMUL(suffix, mul_element, prod_element) \
+  VMUL_DO(mule##suffix, mul_element, prod_element, 1) \
+  VMUL_DO(mulo##suffix, mul_element, prod_element, 0)
+VMUL(sb, s8, s16)
+VMUL(sh, s16, s32)
+VMUL(ub, u8, u16)
+VMUL(uh, u16, u32)
+#undef VMUL_DO
+#undef VMUL
+
 #undef VECTOR_FOR
 #undef VECTOR_FOR_I
 #undef VECTOR_FOR_INORDER_I
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 5b4c5cd..2d4ffbb 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6181,6 +6181,14 @@ GEN_VXFORM(vmrghw, 140);
 GEN_VXFORM(vmrglb, 268);
 GEN_VXFORM(vmrglh, 332);
 GEN_VXFORM(vmrglw, 396);
+GEN_VXFORM(vmuloub, 8);
+GEN_VXFORM(vmulouh, 72);
+GEN_VXFORM(vmulosb, 264);
+GEN_VXFORM(vmulosh, 328);
+GEN_VXFORM(vmuleub, 520);
+GEN_VXFORM(vmuleuh, 584);
+GEN_VXFORM(vmulesb, 776);
+GEN_VXFORM(vmulesh, 840);
 
 #define GEN_VXRFORM1(opname, name, str, xo, rc)                         \
     GEN_HANDLER2(name, str, 0x4, (xo >> 1) & 0x1f, ((xo >> 6) & 0x1f) | (rc << 4), 0x00000000, PPC_ALTIVEC) \
-- 
1.6.0.5