From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LCLpU-0007zq-UI for qemu-devel@nongnu.org; Mon, 15 Dec 2008 17:22:21 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LCLpT-0007z0-Jt for qemu-devel@nongnu.org; Mon, 15 Dec 2008 17:22:20 -0500 Received: from [199.232.76.173] (port=43502 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LCLpT-0007yu-BQ for qemu-devel@nongnu.org; Mon, 15 Dec 2008 17:22:19 -0500 Received: from mx20.gnu.org ([199.232.41.8]:58595) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LCLpT-00022c-5y for qemu-devel@nongnu.org; Mon, 15 Dec 2008 17:22:19 -0500 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LCLpS-00051N-Az for qemu-devel@nongnu.org; Mon, 15 Dec 2008 17:22:18 -0500 From: Nathan Froyd Date: Mon, 15 Dec 2008 14:15:34 -0800 Message-Id: <1229379335-8782-3-git-send-email-froydnj@codesourcery.com> In-Reply-To: <1229379335-8782-1-git-send-email-froydnj@codesourcery.com> References: <1229379335-8782-1-git-send-email-froydnj@codesourcery.com> Subject: [Qemu-devel] [PATCH 19/42] target-ppc: add m{f, t}vscr instructions. Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Signed-off-by: Nathan Froyd --- target-ppc/translate.c | 37 +++++++++++++++++++++++++++++++++++++ 1 files changed, 37 insertions(+), 0 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 791f76b..e72ff33 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -6148,6 +6148,43 @@ GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC) tcg_temp_free(rd); } +static always_inline uint32_t gen_vscr_offset (int r) +{ +#if defined(WORDS_BIGENDIAN) + return offsetof(CPUPPCState, avr[r].u32[3]); +#else + return offsetof(CPUPPCState, avr[r].u32[0]); +#endif +} + +GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC) +{ + TCGv_i32 t; + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0); + tcg_gen_movi_i64(cpu_avrl[rD(ctx->opcode)], 0); + t = tcg_temp_new_i32(); + tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr)); + tcg_gen_st_i32(t, cpu_env, gen_vscr_offset(rD(ctx->opcode))); + tcg_temp_free_i32(t); +} + +GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC) +{ + TCGv_i32 t; + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + t = tcg_temp_new_i32(); + tcg_gen_ld_i32(t, cpu_env, gen_vscr_offset(rB(ctx->opcode))); + tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, vscr)); + tcg_temp_free(t); +} + /* Logical operations */ #define GEN_VX_LOGICAL(name, tcg_op, xo) \ GEN_HANDLER(name, 0x04, (xo >> 1) & 0x1f, (xo >> 6) & 0x1f, 0x00000000, PPC_ALTIVEC) \ -- 1.6.0.5