From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LCbzs-0006Xt-2q for qemu-devel@nongnu.org; Tue, 16 Dec 2008 10:38:08 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LCbzp-0006Wh-HL for qemu-devel@nongnu.org; Tue, 16 Dec 2008 10:38:07 -0500 Received: from [199.232.76.173] (port=34026 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LCbzp-0006Wb-6Y for qemu-devel@nongnu.org; Tue, 16 Dec 2008 10:38:05 -0500 Received: from e32.co.us.ibm.com ([32.97.110.150]:49429) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LCbzo-0005YB-My for qemu-devel@nongnu.org; Tue, 16 Dec 2008 10:38:04 -0500 Received: from d03relay04.boulder.ibm.com (d03relay04.boulder.ibm.com [9.17.195.106]) by e32.co.us.ibm.com (8.13.1/8.13.1) with ESMTP id mBGFaUs6014688 for ; Tue, 16 Dec 2008 08:36:30 -0700 Received: from d03av04.boulder.ibm.com (d03av04.boulder.ibm.com [9.17.195.170]) by d03relay04.boulder.ibm.com (8.13.8/8.13.8/NCO v9.1) with ESMTP id mBGFc13b226230 for ; Tue, 16 Dec 2008 08:38:01 -0700 Received: from d03av04.boulder.ibm.com (loopback [127.0.0.1]) by d03av04.boulder.ibm.com (8.12.11.20060308/8.13.3) with ESMTP id mBGFbxjR001441 for ; Tue, 16 Dec 2008 08:38:01 -0700 Subject: Re: [Qemu-devel] [PATCH 3/4] PowerPC 440EP SoC emulation From: Hollis Blanchard In-Reply-To: <20081216104556.GB20364@volta.aurel32.net> References: <0ae290b3af6b4f088661329e048330cb87c0b828.1229386539.git.hollisb@us.ibm.com> <78d78f687f97d7be0f231035228eee921a25c383.1229386539.git.hollisb@us.ibm.com> <20081216104556.GB20364@volta.aurel32.net> Content-Type: text/plain Date: Tue, 16 Dec 2008 09:37:58 -0600 Message-Id: <1229441878.31337.35.camel@localhost.localdomain> Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno Cc: qemu-devel@nongnu.org, kvm-ppc@vger.kernel.org On Tue, 2008-12-16 at 11:45 +0100, Aurelien Jarno wrote: > On Mon, Dec 15, 2008 at 06:17:31PM -0600, Hollis Blanchard wrote: > > Wire up the system-on-chip devices present on 440EP chips. > > > > This patch is a little unusual in that qemu doesn't actually emulate the 440 > > core, but we use this board code with KVM (which does). If/when 440 core > > emulation is supported, the kvm_enabled() hack can be removed. > > > > What are the mains differences between 405 and 440 cores? Would it be > easy to add support for 440 core in QEMU? It's been a while since I programmed for the 405, but from memory: Unlike the 405, the 440 is a Book E core. The biggest difference is that there is no real mode; MMU translation is always active. MSR[IR] and DR have been replaced with IS and DS, and those "address space" bits contribute to the 41-bit virtual address (32-bit effective, 8-bit PID like 405, 1-bit AS). The TLB organization is pretty much the same as 405 (64-entry fully associative), though the data in each entry has changed a little. Fixed interrupt vectors have been replaced with programmable ones, via the IVPR base register and 16 IVOR registers, indicating the offset of each vector from IVPR. There is a Application Note that more fully lists the software differences: https://www.amcc.com/MyAMCC/retrieveDocument/PowerPC/440GP/PPC440GP_AN2020_SWC405GP.pdf Because the MMU is always on, tlbia doesn't exist any more. There are a few other minor instruction and register changes. As I've mentioned, most 440 peripherals are the same or similar to 405, which is definitely helpful. -- Hollis Blanchard IBM Linux Technology Center