From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LCc33-0007mV-Ko for qemu-devel@nongnu.org; Tue, 16 Dec 2008 10:41:25 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LCc2z-0007kG-Qe for qemu-devel@nongnu.org; Tue, 16 Dec 2008 10:41:25 -0500 Received: from [199.232.76.173] (port=34150 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LCc2z-0007k7-Jh for qemu-devel@nongnu.org; Tue, 16 Dec 2008 10:41:21 -0500 Received: from hera.kernel.org ([140.211.167.34]:45821) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LCc2y-00064H-Vm for qemu-devel@nongnu.org; Tue, 16 Dec 2008 10:41:21 -0500 From: Amit Shah Date: Tue, 16 Dec 2008 15:41:14 +0000 Message-Id: <1229442074-15153-2-git-send-email-amit.shah@redhat.com> In-Reply-To: <1229442074-15153-1-git-send-email-amit.shah@redhat.com> References: <1229442074-15153-1-git-send-email-amit.shah@redhat.com> Subject: [Qemu-devel] [PATCH] QEMU: Mask writes to RO bits in the command reg of PCI config space Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Amit Shah The Command register in the PCI config space has some read-only bits. Any writes to those bits should be masked out. Signed-off-by: Amit Shah --- qemu/hw/pci.c | 3 +++ qemu/hw/pci.h | 5 +++++ 2 files changed, 8 insertions(+), 0 deletions(-) diff --git a/qemu/hw/pci.c b/qemu/hw/pci.c index f07892e..6ba8378 100644 --- a/qemu/hw/pci.c +++ b/qemu/hw/pci.c @@ -452,6 +452,9 @@ void pci_default_write_config(PCIDevice *d, if (can_write) { /* Mask out writes to reserved bits in registers */ switch (addr) { + case 0x05: + val &= ~PCI_COMMAND_RESERVED_MASK_HI; + break; case 0x06: val &= ~PCI_STATUS_RESERVED_MASK_LO; break; diff --git a/qemu/hw/pci.h b/qemu/hw/pci.h index d25b0ca..35cc1e6 100644 --- a/qemu/hw/pci.h +++ b/qemu/hw/pci.h @@ -61,6 +61,11 @@ typedef struct PCIIORegion { #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8) +/* Bits in the PCI Command Register (PCI 2.3 spec) */ +#define PCI_COMMAND_RESERVED 0xf800 + +#define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8) + struct PCIDevice { /* PCI config space */ uint8_t config[256]; -- 1.5.6.3