* [Qemu-devel] [PATCH 01/40] Fix TCG error in gen_avr_ptr.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
@ 2008-12-31 3:09 ` Nathan Froyd
2009-01-03 13:31 ` Aurelien Jarno
2008-12-31 3:09 ` [Qemu-devel] [PATCH 02/40] Add helper macros for later patches Nathan Froyd
` (39 subsequent siblings)
40 siblings, 1 reply; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:09 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/translate.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 80a08b1..7ba9c26 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6085,7 +6085,7 @@ GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
static always_inline TCGv_ptr gen_avr_ptr(int reg)
{
- TCGv_ptr r = tcg_temp_new();
+ TCGv_ptr r = tcg_temp_new_ptr();
tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
return r;
}
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH 01/40] Fix TCG error in gen_avr_ptr.
2008-12-31 3:09 ` [Qemu-devel] [PATCH 01/40] Fix TCG error in gen_avr_ptr Nathan Froyd
@ 2009-01-03 13:31 ` Aurelien Jarno
0 siblings, 0 replies; 68+ messages in thread
From: Aurelien Jarno @ 2009-01-03 13:31 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Tue, Dec 30, 2008 at 07:09:43PM -0800, Nathan Froyd wrote:
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
Thanks, applied.
> target-ppc/translate.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 80a08b1..7ba9c26 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6085,7 +6085,7 @@ GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
>
> static always_inline TCGv_ptr gen_avr_ptr(int reg)
> {
> - TCGv_ptr r = tcg_temp_new();
> + TCGv_ptr r = tcg_temp_new_ptr();
> tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
> return r;
> }
> --
> 1.6.0.5
>
>
>
>
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 02/40] Add helper macros for later patches.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
2008-12-31 3:09 ` [Qemu-devel] [PATCH 01/40] Fix TCG error in gen_avr_ptr Nathan Froyd
@ 2008-12-31 3:09 ` Nathan Froyd
2009-01-03 13:32 ` Aurelien Jarno
2008-12-31 3:09 ` [Qemu-devel] [PATCH 03/40] Add GEN_VXFORM macro for subsequent instructions Nathan Froyd
` (38 subsequent siblings)
40 siblings, 1 reply; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:09 UTC (permalink / raw)
To: qemu-devel
Remove N_ELEMS, VECTOR_FOR, and VECTOR_FOR_I macros. Retain the
VECTOR_FOR_INORDER_I macros as the clearest way of expressing the intent
of iterating over elements in their stored target-endian order.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/op_helper.c | 22 ++++++++++++++++++++++
1 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 876b517..5d603ba 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -1954,6 +1954,28 @@ target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_
}
/*****************************************************************************/
+/* Altivec extension helpers */
+#if defined(WORDS_BIGENDIAN)
+#define HI_IDX 0
+#define LO_IDX 1
+#else
+#define HI_IDX 1
+#define LO_IDX 0
+#endif
+
+#if defined(WORDS_BIGENDIAN)
+#define VECTOR_FOR_INORDER_I(index, element) \
+ for (index = 0; index < ARRAY_SIZE(r->element); index++)
+#else
+#define VECTOR_FOR_INORDER_I(index, element) \
+ for (index = ARRAY_SIZE(r->element)-1; index >= 0; index--)
+#endif
+
+#undef VECTOR_FOR_INORDER_I
+#undef HI_IDX
+#undef LO_IDX
+
+/*****************************************************************************/
/* SPE extension helpers */
/* Use a table to make this quicker */
static uint8_t hbrev[16] = {
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH 02/40] Add helper macros for later patches.
2008-12-31 3:09 ` [Qemu-devel] [PATCH 02/40] Add helper macros for later patches Nathan Froyd
@ 2009-01-03 13:32 ` Aurelien Jarno
0 siblings, 0 replies; 68+ messages in thread
From: Aurelien Jarno @ 2009-01-03 13:32 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Tue, Dec 30, 2008 at 07:09:44PM -0800, Nathan Froyd wrote:
> Remove N_ELEMS, VECTOR_FOR, and VECTOR_FOR_I macros. Retain the
> VECTOR_FOR_INORDER_I macros as the clearest way of expressing the intent
> of iterating over elements in their stored target-endian order.
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Thanks, applied.
> ---
> target-ppc/op_helper.c | 22 ++++++++++++++++++++++
> 1 files changed, 22 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index 876b517..5d603ba 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -1954,6 +1954,28 @@ target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_
> }
>
> /*****************************************************************************/
> +/* Altivec extension helpers */
> +#if defined(WORDS_BIGENDIAN)
> +#define HI_IDX 0
> +#define LO_IDX 1
> +#else
> +#define HI_IDX 1
> +#define LO_IDX 0
> +#endif
> +
> +#if defined(WORDS_BIGENDIAN)
> +#define VECTOR_FOR_INORDER_I(index, element) \
> + for (index = 0; index < ARRAY_SIZE(r->element); index++)
> +#else
> +#define VECTOR_FOR_INORDER_I(index, element) \
> + for (index = ARRAY_SIZE(r->element)-1; index >= 0; index--)
> +#endif
> +
> +#undef VECTOR_FOR_INORDER_I
> +#undef HI_IDX
> +#undef LO_IDX
> +
> +/*****************************************************************************/
> /* SPE extension helpers */
> /* Use a table to make this quicker */
> static uint8_t hbrev[16] = {
> --
> 1.6.0.5
>
>
>
>
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 03/40] Add GEN_VXFORM macro for subsequent instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
2008-12-31 3:09 ` [Qemu-devel] [PATCH 01/40] Fix TCG error in gen_avr_ptr Nathan Froyd
2008-12-31 3:09 ` [Qemu-devel] [PATCH 02/40] Add helper macros for later patches Nathan Froyd
@ 2008-12-31 3:09 ` Nathan Froyd
2009-01-03 13:32 ` Aurelien Jarno
2008-12-31 3:09 ` [Qemu-devel] [PATCH 04/40] Add v{add,sub}u{b,h,w}m instructions Nathan Froyd
` (37 subsequent siblings)
40 siblings, 1 reply; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:09 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/translate.c | 17 +++++++++++++++++
1 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 7ba9c26..4ae780b 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6164,6 +6164,23 @@ GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
+#define GEN_VXFORM(name, opc2, opc3) \
+GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
+{ \
+ TCGv_ptr ra, rb, rd; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ ra = gen_avr_ptr(rA(ctx->opcode)); \
+ rb = gen_avr_ptr(rB(ctx->opcode)); \
+ rd = gen_avr_ptr(rD(ctx->opcode)); \
+ gen_helper_##name (rd, ra, rb); \
+ tcg_temp_free_ptr(ra); \
+ tcg_temp_free_ptr(rb); \
+ tcg_temp_free_ptr(rd); \
+}
+
/*** SPE extension ***/
/* Register moves */
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH 03/40] Add GEN_VXFORM macro for subsequent instructions.
2008-12-31 3:09 ` [Qemu-devel] [PATCH 03/40] Add GEN_VXFORM macro for subsequent instructions Nathan Froyd
@ 2009-01-03 13:32 ` Aurelien Jarno
0 siblings, 0 replies; 68+ messages in thread
From: Aurelien Jarno @ 2009-01-03 13:32 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Tue, Dec 30, 2008 at 07:09:45PM -0800, Nathan Froyd wrote:
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/translate.c | 17 +++++++++++++++++
> 1 files changed, 17 insertions(+), 0 deletions(-)
Thanks, applied.
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 7ba9c26..4ae780b 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6164,6 +6164,23 @@ GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
> GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
> GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
>
> +#define GEN_VXFORM(name, opc2, opc3) \
> +GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
> +{ \
> + TCGv_ptr ra, rb, rd; \
> + if (unlikely(!ctx->altivec_enabled)) { \
> + gen_exception(ctx, POWERPC_EXCP_VPU); \
> + return; \
> + } \
> + ra = gen_avr_ptr(rA(ctx->opcode)); \
> + rb = gen_avr_ptr(rB(ctx->opcode)); \
> + rd = gen_avr_ptr(rD(ctx->opcode)); \
> + gen_helper_##name (rd, ra, rb); \
> + tcg_temp_free_ptr(ra); \
> + tcg_temp_free_ptr(rb); \
> + tcg_temp_free_ptr(rd); \
> +}
> +
> /*** SPE extension ***/
> /* Register moves */
>
> --
> 1.6.0.5
>
>
>
>
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 04/40] Add v{add,sub}u{b,h,w}m instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (2 preceding siblings ...)
2008-12-31 3:09 ` [Qemu-devel] [PATCH 03/40] Add GEN_VXFORM macro for subsequent instructions Nathan Froyd
@ 2008-12-31 3:09 ` Nathan Froyd
2009-01-03 13:33 ` Aurelien Jarno
2008-12-31 3:09 ` [Qemu-devel] [PATCH 05/40] Add vavg{s,u}{b,h,w} instructions Nathan Froyd
` (36 subsequent siblings)
40 siblings, 1 reply; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:09 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 9 +++++++++
target-ppc/op_helper.c | 17 +++++++++++++++++
target-ppc/translate.c | 6 ++++++
3 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 6b5728c..e69fceb 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -96,6 +96,15 @@ DEF_HELPER_1(fres, i64, i64)
DEF_HELPER_1(frsqrte, i64, i64)
DEF_HELPER_3(fsel, i64, i64, i64, i64)
+#define dh_alias_avr ptr
+#define dh_ctype_avr ppc_avr_t *
+
+DEF_HELPER_3(vaddubm, void, avr, avr, avr)
+DEF_HELPER_3(vadduhm, void, avr, avr, avr)
+DEF_HELPER_3(vadduwm, void, avr, avr, avr)
+DEF_HELPER_3(vsububm, void, avr, avr, avr)
+DEF_HELPER_3(vsubuhm, void, avr, avr, avr)
+DEF_HELPER_3(vsubuwm, void, avr, avr, avr)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
DEF_HELPER_1(efscfuf, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 5d603ba..6d4bd1e 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -1971,6 +1971,23 @@ target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_
for (index = ARRAY_SIZE(r->element)-1; index >= 0; index--)
#endif
+#define VARITH_DO(name, op, element) \
+void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+{ \
+ int i; \
+ for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
+ r->element[i] = a->element[i] op b->element[i]; \
+ } \
+}
+#define VARITH(suffix, element) \
+ VARITH_DO(add##suffix, +, element) \
+ VARITH_DO(sub##suffix, -, element)
+VARITH(ubm, u8)
+VARITH(uhm, u16)
+VARITH(uwm, u32)
+#undef VARITH_DO
+#undef VARITH
+
#undef VECTOR_FOR_INORDER_I
#undef HI_IDX
#undef LO_IDX
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 4ae780b..a35ff1a 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6181,6 +6181,12 @@ GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
tcg_temp_free_ptr(rd); \
}
+GEN_VXFORM(vaddubm, 0, 0);
+GEN_VXFORM(vadduhm, 0, 1);
+GEN_VXFORM(vadduwm, 0, 2);
+GEN_VXFORM(vsububm, 0, 16);
+GEN_VXFORM(vsubuhm, 0, 17);
+GEN_VXFORM(vsubuwm, 0, 18);
/*** SPE extension ***/
/* Register moves */
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH 04/40] Add v{add,sub}u{b,h,w}m instructions.
2008-12-31 3:09 ` [Qemu-devel] [PATCH 04/40] Add v{add,sub}u{b,h,w}m instructions Nathan Froyd
@ 2009-01-03 13:33 ` Aurelien Jarno
0 siblings, 0 replies; 68+ messages in thread
From: Aurelien Jarno @ 2009-01-03 13:33 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Tue, Dec 30, 2008 at 07:09:46PM -0800, Nathan Froyd wrote:
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/helper.h | 9 +++++++++
> target-ppc/op_helper.c | 17 +++++++++++++++++
> target-ppc/translate.c | 6 ++++++
> 3 files changed, 32 insertions(+), 0 deletions(-)
Thanks, applied.
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 6b5728c..e69fceb 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -96,6 +96,15 @@ DEF_HELPER_1(fres, i64, i64)
> DEF_HELPER_1(frsqrte, i64, i64)
> DEF_HELPER_3(fsel, i64, i64, i64, i64)
>
> +#define dh_alias_avr ptr
> +#define dh_ctype_avr ppc_avr_t *
> +
> +DEF_HELPER_3(vaddubm, void, avr, avr, avr)
> +DEF_HELPER_3(vadduhm, void, avr, avr, avr)
> +DEF_HELPER_3(vadduwm, void, avr, avr, avr)
> +DEF_HELPER_3(vsububm, void, avr, avr, avr)
> +DEF_HELPER_3(vsubuhm, void, avr, avr, avr)
> +DEF_HELPER_3(vsubuwm, void, avr, avr, avr)
> DEF_HELPER_1(efscfsi, i32, i32)
> DEF_HELPER_1(efscfui, i32, i32)
> DEF_HELPER_1(efscfuf, i32, i32)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index 5d603ba..6d4bd1e 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -1971,6 +1971,23 @@ target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_
> for (index = ARRAY_SIZE(r->element)-1; index >= 0; index--)
> #endif
>
> +#define VARITH_DO(name, op, element) \
> +void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> +{ \
> + int i; \
> + for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
> + r->element[i] = a->element[i] op b->element[i]; \
> + } \
> +}
> +#define VARITH(suffix, element) \
> + VARITH_DO(add##suffix, +, element) \
> + VARITH_DO(sub##suffix, -, element)
> +VARITH(ubm, u8)
> +VARITH(uhm, u16)
> +VARITH(uwm, u32)
> +#undef VARITH_DO
> +#undef VARITH
> +
> #undef VECTOR_FOR_INORDER_I
> #undef HI_IDX
> #undef LO_IDX
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 4ae780b..a35ff1a 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6181,6 +6181,12 @@ GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
> tcg_temp_free_ptr(rd); \
> }
>
> +GEN_VXFORM(vaddubm, 0, 0);
> +GEN_VXFORM(vadduhm, 0, 1);
> +GEN_VXFORM(vadduwm, 0, 2);
> +GEN_VXFORM(vsububm, 0, 16);
> +GEN_VXFORM(vsubuhm, 0, 17);
> +GEN_VXFORM(vsubuwm, 0, 18);
> /*** SPE extension ***/
> /* Register moves */
>
> --
> 1.6.0.5
>
>
>
>
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 05/40] Add vavg{s,u}{b,h,w} instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (3 preceding siblings ...)
2008-12-31 3:09 ` [Qemu-devel] [PATCH 04/40] Add v{add,sub}u{b,h,w}m instructions Nathan Froyd
@ 2008-12-31 3:09 ` Nathan Froyd
2009-01-03 13:33 ` Aurelien Jarno
2008-12-31 3:09 ` [Qemu-devel] [PATCH 06/40] Add v{min, max}{s, u}{b, h, w} instructions Nathan Froyd
` (35 subsequent siblings)
40 siblings, 1 reply; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:09 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 7 +++++++
target-ppc/op_helper.c | 19 +++++++++++++++++++
target-ppc/translate.c | 7 +++++++
3 files changed, 33 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index e69fceb..214bbf1 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -105,6 +105,13 @@ DEF_HELPER_3(vadduwm, void, avr, avr, avr)
DEF_HELPER_3(vsububm, void, avr, avr, avr)
DEF_HELPER_3(vsubuhm, void, avr, avr, avr)
DEF_HELPER_3(vsubuwm, void, avr, avr, avr)
+DEF_HELPER_3(vavgub, void, avr, avr, avr)
+DEF_HELPER_3(vavguh, void, avr, avr, avr)
+DEF_HELPER_3(vavguw, void, avr, avr, avr)
+DEF_HELPER_3(vavgsb, void, avr, avr, avr)
+DEF_HELPER_3(vavgsh, void, avr, avr, avr)
+DEF_HELPER_3(vavgsw, void, avr, avr, avr)
+
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
DEF_HELPER_1(efscfuf, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 6d4bd1e..8f2508f 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -1988,6 +1988,25 @@ VARITH(uwm, u32)
#undef VARITH_DO
#undef VARITH
+#define VAVG_DO(name, element, etype) \
+ void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+ { \
+ int i; \
+ for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
+ etype x = (etype)a->element[i] + (etype)b->element[i] + 1; \
+ r->element[i] = x >> 1; \
+ } \
+ }
+
+#define VAVG(type, signed_element, signed_type, unsigned_element, unsigned_type) \
+ VAVG_DO(avgs##type, signed_element, signed_type) \
+ VAVG_DO(avgu##type, unsigned_element, unsigned_type)
+VAVG(b, s8, int16_t, u8, uint16_t)
+VAVG(h, s16, int32_t, u16, uint32_t)
+VAVG(w, s32, int64_t, u32, uint64_t)
+#undef VAVG_DO
+#undef VAVG
+
#undef VECTOR_FOR_INORDER_I
#undef HI_IDX
#undef LO_IDX
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index a35ff1a..1ccd37e 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6187,6 +6187,13 @@ GEN_VXFORM(vadduwm, 0, 2);
GEN_VXFORM(vsububm, 0, 16);
GEN_VXFORM(vsubuhm, 0, 17);
GEN_VXFORM(vsubuwm, 0, 18);
+GEN_VXFORM(vavgub, 1, 16);
+GEN_VXFORM(vavguh, 1, 17);
+GEN_VXFORM(vavguw, 1, 18);
+GEN_VXFORM(vavgsb, 1, 20);
+GEN_VXFORM(vavgsh, 1, 21);
+GEN_VXFORM(vavgsw, 1, 22);
+
/*** SPE extension ***/
/* Register moves */
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH 05/40] Add vavg{s,u}{b,h,w} instructions.
2008-12-31 3:09 ` [Qemu-devel] [PATCH 05/40] Add vavg{s,u}{b,h,w} instructions Nathan Froyd
@ 2009-01-03 13:33 ` Aurelien Jarno
0 siblings, 0 replies; 68+ messages in thread
From: Aurelien Jarno @ 2009-01-03 13:33 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Tue, Dec 30, 2008 at 07:09:47PM -0800, Nathan Froyd wrote:
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/helper.h | 7 +++++++
> target-ppc/op_helper.c | 19 +++++++++++++++++++
> target-ppc/translate.c | 7 +++++++
> 3 files changed, 33 insertions(+), 0 deletions(-)
Thanks, applied.
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index e69fceb..214bbf1 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -105,6 +105,13 @@ DEF_HELPER_3(vadduwm, void, avr, avr, avr)
> DEF_HELPER_3(vsububm, void, avr, avr, avr)
> DEF_HELPER_3(vsubuhm, void, avr, avr, avr)
> DEF_HELPER_3(vsubuwm, void, avr, avr, avr)
> +DEF_HELPER_3(vavgub, void, avr, avr, avr)
> +DEF_HELPER_3(vavguh, void, avr, avr, avr)
> +DEF_HELPER_3(vavguw, void, avr, avr, avr)
> +DEF_HELPER_3(vavgsb, void, avr, avr, avr)
> +DEF_HELPER_3(vavgsh, void, avr, avr, avr)
> +DEF_HELPER_3(vavgsw, void, avr, avr, avr)
> +
> DEF_HELPER_1(efscfsi, i32, i32)
> DEF_HELPER_1(efscfui, i32, i32)
> DEF_HELPER_1(efscfuf, i32, i32)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index 6d4bd1e..8f2508f 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -1988,6 +1988,25 @@ VARITH(uwm, u32)
> #undef VARITH_DO
> #undef VARITH
>
> +#define VAVG_DO(name, element, etype) \
> + void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> + { \
> + int i; \
> + for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
> + etype x = (etype)a->element[i] + (etype)b->element[i] + 1; \
> + r->element[i] = x >> 1; \
> + } \
> + }
> +
> +#define VAVG(type, signed_element, signed_type, unsigned_element, unsigned_type) \
> + VAVG_DO(avgs##type, signed_element, signed_type) \
> + VAVG_DO(avgu##type, unsigned_element, unsigned_type)
> +VAVG(b, s8, int16_t, u8, uint16_t)
> +VAVG(h, s16, int32_t, u16, uint32_t)
> +VAVG(w, s32, int64_t, u32, uint64_t)
> +#undef VAVG_DO
> +#undef VAVG
> +
> #undef VECTOR_FOR_INORDER_I
> #undef HI_IDX
> #undef LO_IDX
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index a35ff1a..1ccd37e 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6187,6 +6187,13 @@ GEN_VXFORM(vadduwm, 0, 2);
> GEN_VXFORM(vsububm, 0, 16);
> GEN_VXFORM(vsubuhm, 0, 17);
> GEN_VXFORM(vsubuwm, 0, 18);
> +GEN_VXFORM(vavgub, 1, 16);
> +GEN_VXFORM(vavguh, 1, 17);
> +GEN_VXFORM(vavguw, 1, 18);
> +GEN_VXFORM(vavgsb, 1, 20);
> +GEN_VXFORM(vavgsh, 1, 21);
> +GEN_VXFORM(vavgsw, 1, 22);
> +
> /*** SPE extension ***/
> /* Register moves */
>
> --
> 1.6.0.5
>
>
>
>
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 06/40] Add v{min, max}{s, u}{b, h, w} instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (4 preceding siblings ...)
2008-12-31 3:09 ` [Qemu-devel] [PATCH 05/40] Add vavg{s,u}{b,h,w} instructions Nathan Froyd
@ 2008-12-31 3:09 ` Nathan Froyd
2009-01-03 13:33 ` Aurelien Jarno
2008-12-31 3:09 ` [Qemu-devel] [PATCH 07/40] Add GEN_VXRFORM{, 1} macros for subsequent instructions Nathan Froyd
` (34 subsequent siblings)
40 siblings, 1 reply; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:09 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 12 ++++++++++++
target-ppc/op_helper.c | 24 ++++++++++++++++++++++++
target-ppc/translate.c | 12 ++++++++++++
3 files changed, 48 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 214bbf1..196106e 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -111,6 +111,18 @@ DEF_HELPER_3(vavguw, void, avr, avr, avr)
DEF_HELPER_3(vavgsb, void, avr, avr, avr)
DEF_HELPER_3(vavgsh, void, avr, avr, avr)
DEF_HELPER_3(vavgsw, void, avr, avr, avr)
+DEF_HELPER_3(vminsb, void, avr, avr, avr)
+DEF_HELPER_3(vminsh, void, avr, avr, avr)
+DEF_HELPER_3(vminsw, void, avr, avr, avr)
+DEF_HELPER_3(vmaxsb, void, avr, avr, avr)
+DEF_HELPER_3(vmaxsh, void, avr, avr, avr)
+DEF_HELPER_3(vmaxsw, void, avr, avr, avr)
+DEF_HELPER_3(vminub, void, avr, avr, avr)
+DEF_HELPER_3(vminuh, void, avr, avr, avr)
+DEF_HELPER_3(vminuw, void, avr, avr, avr)
+DEF_HELPER_3(vmaxub, void, avr, avr, avr)
+DEF_HELPER_3(vmaxuh, void, avr, avr, avr)
+DEF_HELPER_3(vmaxuw, void, avr, avr, avr)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 8f2508f..367c366 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2007,6 +2007,30 @@ VAVG(w, s32, int64_t, u32, uint64_t)
#undef VAVG_DO
#undef VAVG
+#define VMINMAX_DO(name, compare, element) \
+ void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+ { \
+ int i; \
+ for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
+ if (a->element[i] compare b->element[i]) { \
+ r->element[i] = b->element[i]; \
+ } else { \
+ r->element[i] = a->element[i]; \
+ } \
+ } \
+ }
+#define VMINMAX(suffix, element) \
+ VMINMAX_DO(min##suffix, >, element) \
+ VMINMAX_DO(max##suffix, <, element)
+VMINMAX(sb, s8)
+VMINMAX(sh, s16)
+VMINMAX(sw, s32)
+VMINMAX(ub, u8)
+VMINMAX(uh, u16)
+VMINMAX(uw, u32)
+#undef VMINMAX_DO
+#undef VMINMAX
+
#undef VECTOR_FOR_INORDER_I
#undef HI_IDX
#undef LO_IDX
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 1ccd37e..56d5c51 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6187,6 +6187,18 @@ GEN_VXFORM(vadduwm, 0, 2);
GEN_VXFORM(vsububm, 0, 16);
GEN_VXFORM(vsubuhm, 0, 17);
GEN_VXFORM(vsubuwm, 0, 18);
+GEN_VXFORM(vmaxub, 1, 0);
+GEN_VXFORM(vmaxuh, 1, 1);
+GEN_VXFORM(vmaxuw, 1, 2);
+GEN_VXFORM(vmaxsb, 1, 4);
+GEN_VXFORM(vmaxsh, 1, 5);
+GEN_VXFORM(vmaxsw, 1, 6);
+GEN_VXFORM(vminub, 1, 8);
+GEN_VXFORM(vminuh, 1, 9);
+GEN_VXFORM(vminuw, 1, 10);
+GEN_VXFORM(vminsb, 1, 12);
+GEN_VXFORM(vminsh, 1, 13);
+GEN_VXFORM(vminsw, 1, 14);
GEN_VXFORM(vavgub, 1, 16);
GEN_VXFORM(vavguh, 1, 17);
GEN_VXFORM(vavguw, 1, 18);
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH 06/40] Add v{min, max}{s, u}{b, h, w} instructions.
2008-12-31 3:09 ` [Qemu-devel] [PATCH 06/40] Add v{min, max}{s, u}{b, h, w} instructions Nathan Froyd
@ 2009-01-03 13:33 ` Aurelien Jarno
0 siblings, 0 replies; 68+ messages in thread
From: Aurelien Jarno @ 2009-01-03 13:33 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Tue, Dec 30, 2008 at 07:09:48PM -0800, Nathan Froyd wrote:
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/helper.h | 12 ++++++++++++
> target-ppc/op_helper.c | 24 ++++++++++++++++++++++++
> target-ppc/translate.c | 12 ++++++++++++
> 3 files changed, 48 insertions(+), 0 deletions(-)
Thanks, applied.
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 214bbf1..196106e 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -111,6 +111,18 @@ DEF_HELPER_3(vavguw, void, avr, avr, avr)
> DEF_HELPER_3(vavgsb, void, avr, avr, avr)
> DEF_HELPER_3(vavgsh, void, avr, avr, avr)
> DEF_HELPER_3(vavgsw, void, avr, avr, avr)
> +DEF_HELPER_3(vminsb, void, avr, avr, avr)
> +DEF_HELPER_3(vminsh, void, avr, avr, avr)
> +DEF_HELPER_3(vminsw, void, avr, avr, avr)
> +DEF_HELPER_3(vmaxsb, void, avr, avr, avr)
> +DEF_HELPER_3(vmaxsh, void, avr, avr, avr)
> +DEF_HELPER_3(vmaxsw, void, avr, avr, avr)
> +DEF_HELPER_3(vminub, void, avr, avr, avr)
> +DEF_HELPER_3(vminuh, void, avr, avr, avr)
> +DEF_HELPER_3(vminuw, void, avr, avr, avr)
> +DEF_HELPER_3(vmaxub, void, avr, avr, avr)
> +DEF_HELPER_3(vmaxuh, void, avr, avr, avr)
> +DEF_HELPER_3(vmaxuw, void, avr, avr, avr)
>
> DEF_HELPER_1(efscfsi, i32, i32)
> DEF_HELPER_1(efscfui, i32, i32)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index 8f2508f..367c366 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2007,6 +2007,30 @@ VAVG(w, s32, int64_t, u32, uint64_t)
> #undef VAVG_DO
> #undef VAVG
>
> +#define VMINMAX_DO(name, compare, element) \
> + void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> + { \
> + int i; \
> + for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
> + if (a->element[i] compare b->element[i]) { \
> + r->element[i] = b->element[i]; \
> + } else { \
> + r->element[i] = a->element[i]; \
> + } \
> + } \
> + }
> +#define VMINMAX(suffix, element) \
> + VMINMAX_DO(min##suffix, >, element) \
> + VMINMAX_DO(max##suffix, <, element)
> +VMINMAX(sb, s8)
> +VMINMAX(sh, s16)
> +VMINMAX(sw, s32)
> +VMINMAX(ub, u8)
> +VMINMAX(uh, u16)
> +VMINMAX(uw, u32)
> +#undef VMINMAX_DO
> +#undef VMINMAX
> +
> #undef VECTOR_FOR_INORDER_I
> #undef HI_IDX
> #undef LO_IDX
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 1ccd37e..56d5c51 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6187,6 +6187,18 @@ GEN_VXFORM(vadduwm, 0, 2);
> GEN_VXFORM(vsububm, 0, 16);
> GEN_VXFORM(vsubuhm, 0, 17);
> GEN_VXFORM(vsubuwm, 0, 18);
> +GEN_VXFORM(vmaxub, 1, 0);
> +GEN_VXFORM(vmaxuh, 1, 1);
> +GEN_VXFORM(vmaxuw, 1, 2);
> +GEN_VXFORM(vmaxsb, 1, 4);
> +GEN_VXFORM(vmaxsh, 1, 5);
> +GEN_VXFORM(vmaxsw, 1, 6);
> +GEN_VXFORM(vminub, 1, 8);
> +GEN_VXFORM(vminuh, 1, 9);
> +GEN_VXFORM(vminuw, 1, 10);
> +GEN_VXFORM(vminsb, 1, 12);
> +GEN_VXFORM(vminsh, 1, 13);
> +GEN_VXFORM(vminsw, 1, 14);
> GEN_VXFORM(vavgub, 1, 16);
> GEN_VXFORM(vavguh, 1, 17);
> GEN_VXFORM(vavguw, 1, 18);
> --
> 1.6.0.5
>
>
>
>
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 07/40] Add GEN_VXRFORM{, 1} macros for subsequent instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (5 preceding siblings ...)
2008-12-31 3:09 ` [Qemu-devel] [PATCH 06/40] Add v{min, max}{s, u}{b, h, w} instructions Nathan Froyd
@ 2008-12-31 3:09 ` Nathan Froyd
2009-01-03 13:58 ` Aurelien Jarno
2008-12-31 3:09 ` [Qemu-devel] [PATCH 08/40] Add vcmpequ{b, h, w} and vcmpgt{s, u}{b, h, w} instructions Nathan Froyd
` (33 subsequent siblings)
40 siblings, 1 reply; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:09 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/translate.c | 27 +++++++++++++++++++++++++++
1 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 56d5c51..967d9da 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6206,6 +6206,33 @@ GEN_VXFORM(vavgsb, 1, 20);
GEN_VXFORM(vavgsh, 1, 21);
GEN_VXFORM(vavgsw, 1, 22);
+#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
+ GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
+ { \
+ TCGv_ptr ra, rb, rd; \
+ TCGv_i32 result; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ ra = gen_avr_ptr(rA(ctx->opcode)); \
+ rb = gen_avr_ptr(rB(ctx->opcode)); \
+ rd = gen_avr_ptr(rD(ctx->opcode)); \
+ result = tcg_temp_new_i32(); \
+ gen_helper_##opname (result, rd, ra, rb); \
+ if (opc3 & 0x1) { \
+ tcg_gen_mov_i32(cpu_crf[6], result); \
+ } \
+ tcg_temp_free_ptr(ra); \
+ tcg_temp_free_ptr(rb); \
+ tcg_temp_free_ptr(rd); \
+ tcg_temp_free_i32(result); \
+ }
+
+#define GEN_VXRFORM(name, opc2, opc3) \
+ GEN_VXRFORM1(name, name, #name, opc2, opc3) \
+ GEN_VXRFORM1(name, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
+
/*** SPE extension ***/
/* Register moves */
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH 07/40] Add GEN_VXRFORM{, 1} macros for subsequent instructions.
2008-12-31 3:09 ` [Qemu-devel] [PATCH 07/40] Add GEN_VXRFORM{, 1} macros for subsequent instructions Nathan Froyd
@ 2009-01-03 13:58 ` Aurelien Jarno
2009-01-07 21:22 ` Nathan Froyd
0 siblings, 1 reply; 68+ messages in thread
From: Aurelien Jarno @ 2009-01-03 13:58 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Tue, Dec 30, 2008 at 07:09:49PM -0800, Nathan Froyd wrote:
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/translate.c | 27 +++++++++++++++++++++++++++
> 1 files changed, 27 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 56d5c51..967d9da 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6206,6 +6206,33 @@ GEN_VXFORM(vavgsb, 1, 20);
> GEN_VXFORM(vavgsh, 1, 21);
> GEN_VXFORM(vavgsw, 1, 22);
>
> +#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
> + GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
> + { \
> + TCGv_ptr ra, rb, rd; \
> + TCGv_i32 result; \
> + if (unlikely(!ctx->altivec_enabled)) { \
> + gen_exception(ctx, POWERPC_EXCP_VPU); \
> + return; \
> + } \
> + ra = gen_avr_ptr(rA(ctx->opcode)); \
> + rb = gen_avr_ptr(rB(ctx->opcode)); \
> + rd = gen_avr_ptr(rD(ctx->opcode)); \
> + result = tcg_temp_new_i32(); \
> + gen_helper_##opname (result, rd, ra, rb); \
> + if (opc3 & 0x1) { \
This should be opc3 & (0x1 << 4).
> + tcg_gen_mov_i32(cpu_crf[6], result); \
> + } \
By the way, given those functions are using helpers, it may be better to
have one helper for normal functions and one helper for '.' functions
which directly write env->crf[6]. It would probably be a bit faster.
Note that the other PowerPC instructions are maybe not the best
templates for that, given they have been translated from dyngen. I am
planning to fold part of the TCG code directly into the helper for some
of them.
> + tcg_temp_free_ptr(ra); \
> + tcg_temp_free_ptr(rb); \
> + tcg_temp_free_ptr(rd); \
> + tcg_temp_free_i32(result); \
> + }
> +
> +#define GEN_VXRFORM(name, opc2, opc3) \
> + GEN_VXRFORM1(name, name, #name, opc2, opc3) \
> + GEN_VXRFORM1(name, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
> +
> /*** SPE extension ***/
> /* Register moves */
>
> --
> 1.6.0.5
>
>
>
>
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH 07/40] Add GEN_VXRFORM{, 1} macros for subsequent instructions.
2009-01-03 13:58 ` Aurelien Jarno
@ 2009-01-07 21:22 ` Nathan Froyd
2009-01-08 18:55 ` Aurelien Jarno
0 siblings, 1 reply; 68+ messages in thread
From: Nathan Froyd @ 2009-01-07 21:22 UTC (permalink / raw)
To: qemu-devel
On Sat, Jan 03, 2009 at 02:58:03PM +0100, Aurelien Jarno wrote:
> On Tue, Dec 30, 2008 at 07:09:49PM -0800, Nathan Froyd wrote:
> > + if (opc3 & 0x1) { \
>
> This should be opc3 & (0x1 << 4).
I knew I would screw that up, thanks for catching it.
> > + tcg_gen_mov_i32(cpu_crf[6], result); \
> > + } \
>
> By the way, given those functions are using helpers, it may be better to
> have one helper for normal functions and one helper for '.' functions
> which directly write env->crf[6]. It would probably be a bit faster.
I'm ambivalent on this; I think that executing vcmp* instructions
happens infrequently enough that it's probably not worth optimizing them
by computing/writing the result when the record bit is set. But the
patch below (and subsequent incoming patch for the vcmp* instructions)
implements your suggestion.
-Nathan
Use separate helpers for recording and non-recording instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/translate.c | 21 +++++++++++++++++++++
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 03dac58..ee3c747 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6359,6 +6359,27 @@ GEN_VXFORM(vsum4shs, 4, 25);
GEN_VXFORM(vsum2sws, 4, 26);
GEN_VXFORM(vsumsws, 4, 30);
+#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
+ GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
+ { \
+ TCGv_ptr ra, rb, rd; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ ra = gen_avr_ptr(rA(ctx->opcode)); \
+ rb = gen_avr_ptr(rB(ctx->opcode)); \
+ rd = gen_avr_ptr(rD(ctx->opcode)); \
+ gen_helper_##opname (rd, ra, rb); \
+ tcg_temp_free_ptr(ra); \
+ tcg_temp_free_ptr(rb); \
+ tcg_temp_free_ptr(rd); \
+ }
+
+#define GEN_VXRFORM(name, opc2, opc3) \
+ GEN_VXRFORM1(name, name, #name, opc2, opc3) \
+ GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
+
#define GEN_VXFORM_NOA(name, opc2, opc3) \
GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) \
{ \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH 07/40] Add GEN_VXRFORM{, 1} macros for subsequent instructions.
2009-01-07 21:22 ` Nathan Froyd
@ 2009-01-08 18:55 ` Aurelien Jarno
0 siblings, 0 replies; 68+ messages in thread
From: Aurelien Jarno @ 2009-01-08 18:55 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Wed, Jan 07, 2009 at 01:22:11PM -0800, Nathan Froyd wrote:
> On Sat, Jan 03, 2009 at 02:58:03PM +0100, Aurelien Jarno wrote:
> > On Tue, Dec 30, 2008 at 07:09:49PM -0800, Nathan Froyd wrote:
> > > + if (opc3 & 0x1) { \
> >
> > This should be opc3 & (0x1 << 4).
>
> I knew I would screw that up, thanks for catching it.
>
> > > + tcg_gen_mov_i32(cpu_crf[6], result); \
> > > + } \
> >
> > By the way, given those functions are using helpers, it may be better to
> > have one helper for normal functions and one helper for '.' functions
> > which directly write env->crf[6]. It would probably be a bit faster.
>
> I'm ambivalent on this; I think that executing vcmp* instructions
> happens infrequently enough that it's probably not worth optimizing them
> by computing/writing the result when the record bit is set. But the
> patch below (and subsequent incoming patch for the vcmp* instructions)
> implements your suggestion.
>
> -Nathan
>
> Use separate helpers for recording and non-recording instructions.
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Thanks, applied.
> ---
> target-ppc/translate.c | 21 +++++++++++++++++++++
> 1 files changed, 21 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 03dac58..ee3c747 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6359,6 +6359,27 @@ GEN_VXFORM(vsum4shs, 4, 25);
> GEN_VXFORM(vsum2sws, 4, 26);
> GEN_VXFORM(vsumsws, 4, 30);
>
> +#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
> + GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
> + { \
> + TCGv_ptr ra, rb, rd; \
> + if (unlikely(!ctx->altivec_enabled)) { \
> + gen_exception(ctx, POWERPC_EXCP_VPU); \
> + return; \
> + } \
> + ra = gen_avr_ptr(rA(ctx->opcode)); \
> + rb = gen_avr_ptr(rB(ctx->opcode)); \
> + rd = gen_avr_ptr(rD(ctx->opcode)); \
> + gen_helper_##opname (rd, ra, rb); \
> + tcg_temp_free_ptr(ra); \
> + tcg_temp_free_ptr(rb); \
> + tcg_temp_free_ptr(rd); \
> + }
> +
> +#define GEN_VXRFORM(name, opc2, opc3) \
> + GEN_VXRFORM1(name, name, #name, opc2, opc3) \
> + GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
> +
> #define GEN_VXFORM_NOA(name, opc2, opc3) \
> GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) \
> { \
> --
> 1.6.0.5
>
>
>
>
>
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 08/40] Add vcmpequ{b, h, w} and vcmpgt{s, u}{b, h, w} instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (6 preceding siblings ...)
2008-12-31 3:09 ` [Qemu-devel] [PATCH 07/40] Add GEN_VXRFORM{, 1} macros for subsequent instructions Nathan Froyd
@ 2008-12-31 3:09 ` Nathan Froyd
2009-01-03 14:02 ` Aurelien Jarno
2008-12-31 3:09 ` [Qemu-devel] [PATCH 09/40] Add vscr access macros Nathan Froyd
` (32 subsequent siblings)
40 siblings, 1 reply; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:09 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 9 +++++++++
target-ppc/op_helper.c | 34 ++++++++++++++++++++++++++++++++++
target-ppc/translate.c | 10 ++++++++++
3 files changed, 53 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 196106e..efe7a1a 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -123,6 +123,15 @@ DEF_HELPER_3(vminuw, void, avr, avr, avr)
DEF_HELPER_3(vmaxub, void, avr, avr, avr)
DEF_HELPER_3(vmaxuh, void, avr, avr, avr)
DEF_HELPER_3(vmaxuw, void, avr, avr, avr)
+DEF_HELPER_3(vcmpequb, i32, avr, avr, avr)
+DEF_HELPER_3(vcmpequh, i32, avr, avr, avr)
+DEF_HELPER_3(vcmpequw, i32, avr, avr, avr)
+DEF_HELPER_3(vcmpgtub, i32, avr, avr, avr)
+DEF_HELPER_3(vcmpgtuh, i32, avr, avr, avr)
+DEF_HELPER_3(vcmpgtuw, i32, avr, avr, avr)
+DEF_HELPER_3(vcmpgtsb, i32, avr, avr, avr)
+DEF_HELPER_3(vcmpgtsh, i32, avr, avr, avr)
+DEF_HELPER_3(vcmpgtsw, i32, avr, avr, avr)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 367c366..5daa62f 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2007,6 +2007,40 @@ VAVG(w, s32, int64_t, u32, uint64_t)
#undef VAVG_DO
#undef VAVG
+#define VCMP(suffix, compare, element) \
+ uint32_t helper_vcmp##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+ { \
+ uint32_t ones = (sizeof (a->element[0]) == 4 \
+ ? 0xffffffff \
+ : (sizeof (a->element[0]) == 2 \
+ ? 0xffff \
+ : 0xff)); \
+ uint32_t all = ones; \
+ uint32_t none = 0; \
+ int i; \
+ for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
+ uint32_t result = (a->element[i] compare b->element[i] ? ones : 0x0); \
+ switch (sizeof (a->element[0])) { \
+ case 4: r->u32[i] = result; break; \
+ case 2: r->u16[i] = result; break; \
+ case 1: r->u8[i] = result; break; \
+ } \
+ all &= result; \
+ none |= result; \
+ } \
+ return ((all != 0) << 3) | ((none == 0) << 1); \
+ }
+VCMP(equb, ==, u8)
+VCMP(equh, ==, u16)
+VCMP(equw, ==, u32)
+VCMP(gtub, >, u8)
+VCMP(gtuh, >, u16)
+VCMP(gtuw, >, u32)
+VCMP(gtsb, >, s8)
+VCMP(gtsh, >, s16)
+VCMP(gtsw, >, s32)
+#undef VCMP
+
#define VMINMAX_DO(name, compare, element) \
void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 967d9da..7ebdb21 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6233,6 +6233,16 @@ GEN_VXFORM(vavgsw, 1, 22);
GEN_VXRFORM1(name, name, #name, opc2, opc3) \
GEN_VXRFORM1(name, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
+GEN_VXRFORM(vcmpequb, 3, 0)
+GEN_VXRFORM(vcmpequh, 3, 1)
+GEN_VXRFORM(vcmpequw, 3, 2)
+GEN_VXRFORM(vcmpgtsb, 3, 12)
+GEN_VXRFORM(vcmpgtsh, 3, 13)
+GEN_VXRFORM(vcmpgtsw, 3, 14)
+GEN_VXRFORM(vcmpgtub, 3, 8)
+GEN_VXRFORM(vcmpgtuh, 3, 9)
+GEN_VXRFORM(vcmpgtuw, 3, 10)
+
/*** SPE extension ***/
/* Register moves */
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH 08/40] Add vcmpequ{b, h, w} and vcmpgt{s, u}{b, h, w} instructions.
2008-12-31 3:09 ` [Qemu-devel] [PATCH 08/40] Add vcmpequ{b, h, w} and vcmpgt{s, u}{b, h, w} instructions Nathan Froyd
@ 2009-01-03 14:02 ` Aurelien Jarno
2009-01-07 21:23 ` Nathan Froyd
0 siblings, 1 reply; 68+ messages in thread
From: Aurelien Jarno @ 2009-01-03 14:02 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Tue, Dec 30, 2008 at 07:09:50PM -0800, Nathan Froyd wrote:
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/helper.h | 9 +++++++++
> target-ppc/op_helper.c | 34 ++++++++++++++++++++++++++++++++++
> target-ppc/translate.c | 10 ++++++++++
> 3 files changed, 53 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 196106e..efe7a1a 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -123,6 +123,15 @@ DEF_HELPER_3(vminuw, void, avr, avr, avr)
> DEF_HELPER_3(vmaxub, void, avr, avr, avr)
> DEF_HELPER_3(vmaxuh, void, avr, avr, avr)
> DEF_HELPER_3(vmaxuw, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpequb, i32, avr, avr, avr)
> +DEF_HELPER_3(vcmpequh, i32, avr, avr, avr)
> +DEF_HELPER_3(vcmpequw, i32, avr, avr, avr)
> +DEF_HELPER_3(vcmpgtub, i32, avr, avr, avr)
> +DEF_HELPER_3(vcmpgtuh, i32, avr, avr, avr)
> +DEF_HELPER_3(vcmpgtuw, i32, avr, avr, avr)
> +DEF_HELPER_3(vcmpgtsb, i32, avr, avr, avr)
> +DEF_HELPER_3(vcmpgtsh, i32, avr, avr, avr)
> +DEF_HELPER_3(vcmpgtsw, i32, avr, avr, avr)
>
> DEF_HELPER_1(efscfsi, i32, i32)
> DEF_HELPER_1(efscfui, i32, i32)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index 367c366..5daa62f 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2007,6 +2007,40 @@ VAVG(w, s32, int64_t, u32, uint64_t)
> #undef VAVG_DO
> #undef VAVG
>
> +#define VCMP(suffix, compare, element) \
> + uint32_t helper_vcmp##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> + { \
> + uint32_t ones = (sizeof (a->element[0]) == 4 \
> + ? 0xffffffff \
> + : (sizeof (a->element[0]) == 2 \
> + ? 0xffff \
> + : 0xff)); \
> + uint32_t all = ones; \
> + uint32_t none = 0; \
> + int i; \
> + for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
> + uint32_t result = (a->element[i] compare b->element[i] ? ones : 0x0); \
> + switch (sizeof (a->element[0])) { \
> + case 4: r->u32[i] = result; break; \
> + case 2: r->u16[i] = result; break; \
> + case 1: r->u8[i] = result; break; \
> + } \
> + all &= result; \
> + none |= result; \
> + } \
The part defining the ones looks a bit complicated. You may want to
define result as int32_t, and put either -1 or 0. Then you can just cast
the value:
case 4: r->u32[i] = (int32_t)result; break;
case 2: r->u16[i] = (int16_t)result; break;
case 1: r->u8[i] = (int8_t)result; break;
> + return ((all != 0) << 3) | ((none == 0) << 1); \
> + }
> +VCMP(equb, ==, u8)
> +VCMP(equh, ==, u16)
> +VCMP(equw, ==, u32)
> +VCMP(gtub, >, u8)
> +VCMP(gtuh, >, u16)
> +VCMP(gtuw, >, u32)
> +VCMP(gtsb, >, s8)
> +VCMP(gtsh, >, s16)
> +VCMP(gtsw, >, s32)
> +#undef VCMP
> +
> #define VMINMAX_DO(name, compare, element) \
> void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> { \
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 967d9da..7ebdb21 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6233,6 +6233,16 @@ GEN_VXFORM(vavgsw, 1, 22);
> GEN_VXRFORM1(name, name, #name, opc2, opc3) \
> GEN_VXRFORM1(name, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
>
> +GEN_VXRFORM(vcmpequb, 3, 0)
> +GEN_VXRFORM(vcmpequh, 3, 1)
> +GEN_VXRFORM(vcmpequw, 3, 2)
> +GEN_VXRFORM(vcmpgtsb, 3, 12)
> +GEN_VXRFORM(vcmpgtsh, 3, 13)
> +GEN_VXRFORM(vcmpgtsw, 3, 14)
> +GEN_VXRFORM(vcmpgtub, 3, 8)
> +GEN_VXRFORM(vcmpgtuh, 3, 9)
> +GEN_VXRFORM(vcmpgtuw, 3, 10)
> +
> /*** SPE extension ***/
> /* Register moves */
>
> --
> 1.6.0.5
>
>
>
>
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH 08/40] Add vcmpequ{b, h, w} and vcmpgt{s, u}{b, h, w} instructions.
2009-01-03 14:02 ` Aurelien Jarno
@ 2009-01-07 21:23 ` Nathan Froyd
2009-01-08 18:56 ` Aurelien Jarno
0 siblings, 1 reply; 68+ messages in thread
From: Nathan Froyd @ 2009-01-07 21:23 UTC (permalink / raw)
To: qemu-devel
On Sat, Jan 03, 2009 at 03:02:14PM +0100, Aurelien Jarno wrote:
> On Tue, Dec 30, 2008 at 07:09:50PM -0800, Nathan Froyd wrote:
> > +#define VCMP(suffix, compare, element) \
> > + uint32_t helper_vcmp##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> > + { \
> > + uint32_t ones = (sizeof (a->element[0]) == 4 \
> > + ? 0xffffffff \
> > + : (sizeof (a->element[0]) == 2 \
> > + ? 0xffff \
> > + : 0xff)); \
> > + uint32_t all = ones; \
> > + uint32_t none = 0; \
> > + int i; \
> > + for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
> > + uint32_t result = (a->element[i] compare b->element[i] ? ones : 0x0); \
> > + switch (sizeof (a->element[0])) { \
> > + case 4: r->u32[i] = result; break; \
> > + case 2: r->u16[i] = result; break; \
> > + case 1: r->u8[i] = result; break; \
> > + } \
> > + all &= result; \
> > + none |= result; \
> > + } \
>
> The part defining the ones looks a bit complicated. You may want to
> define result as int32_t, and put either -1 or 0. Then you can just cast
> the value:
> case 4: r->u32[i] = (int32_t)result; break;
> case 2: r->u16[i] = (int16_t)result; break;
> case 1: r->u8[i] = (int8_t)result; break;
Done (or something close to it) thusly.
-Nathan
Create separate helpers for record and non-recording versions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 18 ++++++++++++++++++
target-ppc/op_helper.c | 36 ++++++++++++++++++++++++++++++++++++
target-ppc/translate.c | 10 ++++++++++
3 files changed, 64 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index f319fdb..bae137b 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -123,6 +123,24 @@ DEF_HELPER_3(vminuw, void, avr, avr, avr)
DEF_HELPER_3(vmaxub, void, avr, avr, avr)
DEF_HELPER_3(vmaxuh, void, avr, avr, avr)
DEF_HELPER_3(vmaxuw, void, avr, avr, avr)
+DEF_HELPER_3(vcmpequb, void, avr, avr, avr)
+DEF_HELPER_3(vcmpequh, void, avr, avr, avr)
+DEF_HELPER_3(vcmpequw, void, avr, avr, avr)
+DEF_HELPER_3(vcmpgtub, void, avr, avr, avr)
+DEF_HELPER_3(vcmpgtuh, void, avr, avr, avr)
+DEF_HELPER_3(vcmpgtuw, void, avr, avr, avr)
+DEF_HELPER_3(vcmpgtsb, void, avr, avr, avr)
+DEF_HELPER_3(vcmpgtsh, void, avr, avr, avr)
+DEF_HELPER_3(vcmpgtsw, void, avr, avr, avr)
+DEF_HELPER_3(vcmpequb_dot, void, avr, avr, avr)
+DEF_HELPER_3(vcmpequh_dot, void, avr, avr, avr)
+DEF_HELPER_3(vcmpequw_dot, void, avr, avr, avr)
+DEF_HELPER_3(vcmpgtub_dot, void, avr, avr, avr)
+DEF_HELPER_3(vcmpgtuh_dot, void, avr, avr, avr)
+DEF_HELPER_3(vcmpgtuw_dot, void, avr, avr, avr)
+DEF_HELPER_3(vcmpgtsb_dot, void, avr, avr, avr)
+DEF_HELPER_3(vcmpgtsh_dot, void, avr, avr, avr)
+DEF_HELPER_3(vcmpgtsw_dot, void, avr, avr, avr)
DEF_HELPER_3(vmrglb, void, avr, avr, avr)
DEF_HELPER_3(vmrglh, void, avr, avr, avr)
DEF_HELPER_3(vmrglw, void, avr, avr, avr)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 5e40e42..eb155aa 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2101,6 +2101,42 @@ VAVG(w, s32, int64_t, u32, uint64_t)
#undef VAVG_DO
#undef VAVG
+#define VCMP_DO(suffix, compare, element, record) \
+ void helper_vcmp##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+ { \
+ uint32_t ones = (uint32_t)-1; \
+ uint32_t all = ones; \
+ uint32_t none = 0; \
+ int i; \
+ for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
+ uint32_t result = (a->element[i] compare b->element[i] ? ones : 0x0); \
+ switch (sizeof (a->element[0])) { \
+ case 4: r->u32[i] = result; break; \
+ case 2: r->u16[i] = result; break; \
+ case 1: r->u8[i] = result; break; \
+ } \
+ all &= result; \
+ none |= result; \
+ } \
+ if (record) { \
+ env->crf[6] = ((all != 0) << 3) | ((none == 0) << 1); \
+ } \
+ }
+#define VCMP(suffix, compare, element) \
+ VCMP_DO(suffix, compare, element, 0) \
+ VCMP_DO(suffix##_dot, compare, element, 1)
+VCMP(equb, ==, u8)
+VCMP(equh, ==, u16)
+VCMP(equw, ==, u32)
+VCMP(gtub, >, u8)
+VCMP(gtuh, >, u16)
+VCMP(gtuw, >, u32)
+VCMP(gtsb, >, s8)
+VCMP(gtsh, >, s16)
+VCMP(gtsw, >, s32)
+#undef VCMP_DO
+#undef VCMP
+
void helper_vmhaddshs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
{
int sat = 0;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index ee3c747..20e9e0c 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6380,6 +6380,16 @@ GEN_VXFORM(vsumsws, 4, 30);
GEN_VXRFORM1(name, name, #name, opc2, opc3) \
GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
+GEN_VXRFORM(vcmpequb, 3, 0)
+GEN_VXRFORM(vcmpequh, 3, 1)
+GEN_VXRFORM(vcmpequw, 3, 2)
+GEN_VXRFORM(vcmpgtsb, 3, 12)
+GEN_VXRFORM(vcmpgtsh, 3, 13)
+GEN_VXRFORM(vcmpgtsw, 3, 14)
+GEN_VXRFORM(vcmpgtub, 3, 8)
+GEN_VXRFORM(vcmpgtuh, 3, 9)
+GEN_VXRFORM(vcmpgtuw, 3, 10)
+
#define GEN_VXFORM_NOA(name, opc2, opc3) \
GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) \
{ \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH 08/40] Add vcmpequ{b, h, w} and vcmpgt{s, u}{b, h, w} instructions.
2009-01-07 21:23 ` Nathan Froyd
@ 2009-01-08 18:56 ` Aurelien Jarno
0 siblings, 0 replies; 68+ messages in thread
From: Aurelien Jarno @ 2009-01-08 18:56 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Wed, Jan 07, 2009 at 01:23:10PM -0800, Nathan Froyd wrote:
> On Sat, Jan 03, 2009 at 03:02:14PM +0100, Aurelien Jarno wrote:
> > On Tue, Dec 30, 2008 at 07:09:50PM -0800, Nathan Froyd wrote:
> > > +#define VCMP(suffix, compare, element) \
> > > + uint32_t helper_vcmp##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> > > + { \
> > > + uint32_t ones = (sizeof (a->element[0]) == 4 \
> > > + ? 0xffffffff \
> > > + : (sizeof (a->element[0]) == 2 \
> > > + ? 0xffff \
> > > + : 0xff)); \
> > > + uint32_t all = ones; \
> > > + uint32_t none = 0; \
> > > + int i; \
> > > + for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
> > > + uint32_t result = (a->element[i] compare b->element[i] ? ones : 0x0); \
> > > + switch (sizeof (a->element[0])) { \
> > > + case 4: r->u32[i] = result; break; \
> > > + case 2: r->u16[i] = result; break; \
> > > + case 1: r->u8[i] = result; break; \
> > > + } \
> > > + all &= result; \
> > > + none |= result; \
> > > + } \
> >
> > The part defining the ones looks a bit complicated. You may want to
> > define result as int32_t, and put either -1 or 0. Then you can just cast
> > the value:
> > case 4: r->u32[i] = (int32_t)result; break;
> > case 2: r->u16[i] = (int16_t)result; break;
> > case 1: r->u8[i] = (int8_t)result; break;
>
> Done (or something close to it) thusly.
>
> -Nathan
>
> Create separate helpers for record and non-recording versions.
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Thanks, applied.
> ---
> target-ppc/helper.h | 18 ++++++++++++++++++
> target-ppc/op_helper.c | 36 ++++++++++++++++++++++++++++++++++++
> target-ppc/translate.c | 10 ++++++++++
> 3 files changed, 64 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index f319fdb..bae137b 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -123,6 +123,24 @@ DEF_HELPER_3(vminuw, void, avr, avr, avr)
> DEF_HELPER_3(vmaxub, void, avr, avr, avr)
> DEF_HELPER_3(vmaxuh, void, avr, avr, avr)
> DEF_HELPER_3(vmaxuw, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpequb, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpequh, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpequw, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpgtub, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpgtuh, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpgtuw, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpgtsb, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpgtsh, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpgtsw, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpequb_dot, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpequh_dot, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpequw_dot, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpgtub_dot, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpgtuh_dot, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpgtuw_dot, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpgtsb_dot, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpgtsh_dot, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpgtsw_dot, void, avr, avr, avr)
> DEF_HELPER_3(vmrglb, void, avr, avr, avr)
> DEF_HELPER_3(vmrglh, void, avr, avr, avr)
> DEF_HELPER_3(vmrglw, void, avr, avr, avr)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index 5e40e42..eb155aa 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2101,6 +2101,42 @@ VAVG(w, s32, int64_t, u32, uint64_t)
> #undef VAVG_DO
> #undef VAVG
>
> +#define VCMP_DO(suffix, compare, element, record) \
> + void helper_vcmp##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> + { \
> + uint32_t ones = (uint32_t)-1; \
> + uint32_t all = ones; \
> + uint32_t none = 0; \
> + int i; \
> + for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
> + uint32_t result = (a->element[i] compare b->element[i] ? ones : 0x0); \
> + switch (sizeof (a->element[0])) { \
> + case 4: r->u32[i] = result; break; \
> + case 2: r->u16[i] = result; break; \
> + case 1: r->u8[i] = result; break; \
> + } \
> + all &= result; \
> + none |= result; \
> + } \
> + if (record) { \
> + env->crf[6] = ((all != 0) << 3) | ((none == 0) << 1); \
> + } \
> + }
> +#define VCMP(suffix, compare, element) \
> + VCMP_DO(suffix, compare, element, 0) \
> + VCMP_DO(suffix##_dot, compare, element, 1)
> +VCMP(equb, ==, u8)
> +VCMP(equh, ==, u16)
> +VCMP(equw, ==, u32)
> +VCMP(gtub, >, u8)
> +VCMP(gtuh, >, u16)
> +VCMP(gtuw, >, u32)
> +VCMP(gtsb, >, s8)
> +VCMP(gtsh, >, s16)
> +VCMP(gtsw, >, s32)
> +#undef VCMP_DO
> +#undef VCMP
> +
> void helper_vmhaddshs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> {
> int sat = 0;
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index ee3c747..20e9e0c 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6380,6 +6380,16 @@ GEN_VXFORM(vsumsws, 4, 30);
> GEN_VXRFORM1(name, name, #name, opc2, opc3) \
> GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
>
> +GEN_VXRFORM(vcmpequb, 3, 0)
> +GEN_VXRFORM(vcmpequh, 3, 1)
> +GEN_VXRFORM(vcmpequw, 3, 2)
> +GEN_VXRFORM(vcmpgtsb, 3, 12)
> +GEN_VXRFORM(vcmpgtsh, 3, 13)
> +GEN_VXRFORM(vcmpgtsw, 3, 14)
> +GEN_VXRFORM(vcmpgtub, 3, 8)
> +GEN_VXRFORM(vcmpgtuh, 3, 9)
> +GEN_VXRFORM(vcmpgtuw, 3, 10)
> +
> #define GEN_VXFORM_NOA(name, opc2, opc3) \
> GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) \
> { \
> --
> 1.6.0.5
>
>
>
>
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 09/40] Add vscr access macros.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (7 preceding siblings ...)
2008-12-31 3:09 ` [Qemu-devel] [PATCH 08/40] Add vcmpequ{b, h, w} and vcmpgt{s, u}{b, h, w} instructions Nathan Froyd
@ 2008-12-31 3:09 ` Nathan Froyd
2009-01-03 14:04 ` Aurelien Jarno
2008-12-31 3:09 ` [Qemu-devel] [PATCH 10/40] Add vmrg{l,h}{b,h,w} instructions Nathan Froyd
` (31 subsequent siblings)
40 siblings, 1 reply; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:09 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/cpu.h | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index f7600c4..113bba5 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -525,6 +525,13 @@ enum {
0x1F)
/*****************************************************************************/
+/* Vector status and control register */
+#define VSCR_NJ 16 /* Vector non-java */
+#define VSCR_SAT 0 /* Vector saturation */
+#define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
+#define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
+
+/*****************************************************************************/
/* The whole PowerPC CPU context */
#define NB_MMU_MODES 3
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH 09/40] Add vscr access macros.
2008-12-31 3:09 ` [Qemu-devel] [PATCH 09/40] Add vscr access macros Nathan Froyd
@ 2009-01-03 14:04 ` Aurelien Jarno
0 siblings, 0 replies; 68+ messages in thread
From: Aurelien Jarno @ 2009-01-03 14:04 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Tue, Dec 30, 2008 at 07:09:51PM -0800, Nathan Froyd wrote:
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/cpu.h | 7 +++++++
> 1 files changed, 7 insertions(+), 0 deletions(-)
Thanks, applied.
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index f7600c4..113bba5 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -525,6 +525,13 @@ enum {
> 0x1F)
>
> /*****************************************************************************/
> +/* Vector status and control register */
> +#define VSCR_NJ 16 /* Vector non-java */
> +#define VSCR_SAT 0 /* Vector saturation */
> +#define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
> +#define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
> +
> +/*****************************************************************************/
> /* The whole PowerPC CPU context */
> #define NB_MMU_MODES 3
>
> --
> 1.6.0.5
>
>
>
>
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 10/40] Add vmrg{l,h}{b,h,w} instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (8 preceding siblings ...)
2008-12-31 3:09 ` [Qemu-devel] [PATCH 09/40] Add vscr access macros Nathan Froyd
@ 2008-12-31 3:09 ` Nathan Froyd
2008-12-31 3:09 ` [Qemu-devel] [PATCH 11/40] Add vmul{e,o}{s,u}{b,h} instructions Nathan Froyd
` (30 subsequent siblings)
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:09 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 6 ++++++
target-ppc/op_helper.c | 35 +++++++++++++++++++++++++++++++++++
target-ppc/translate.c | 6 ++++++
3 files changed, 47 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index efe7a1a..5a05157 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -123,6 +123,12 @@ DEF_HELPER_3(vminuw, void, avr, avr, avr)
DEF_HELPER_3(vmaxub, void, avr, avr, avr)
DEF_HELPER_3(vmaxuh, void, avr, avr, avr)
DEF_HELPER_3(vmaxuw, void, avr, avr, avr)
+DEF_HELPER_3(vmrglb, void, avr, avr, avr)
+DEF_HELPER_3(vmrglh, void, avr, avr, avr)
+DEF_HELPER_3(vmrglw, void, avr, avr, avr)
+DEF_HELPER_3(vmrghb, void, avr, avr, avr)
+DEF_HELPER_3(vmrghh, void, avr, avr, avr)
+DEF_HELPER_3(vmrghw, void, avr, avr, avr)
DEF_HELPER_3(vcmpequb, i32, avr, avr, avr)
DEF_HELPER_3(vcmpequh, i32, avr, avr, avr)
DEF_HELPER_3(vcmpequw, i32, avr, avr, avr)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 5daa62f..0e502bc 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2065,6 +2065,41 @@ VMINMAX(uw, u32)
#undef VMINMAX_DO
#undef VMINMAX
+#define VMRG_DO(name, element, highp) \
+ void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+ { \
+ ppc_avr_t result; \
+ int i; \
+ size_t n_elems = N_ELEMS(element); \
+ for (i = 0; i < n_elems/2; i++) { \
+ if (highp) { \
+ result.element[i*2+HI_IDX] = a->element[i]; \
+ result.element[i*2+LO_IDX] = b->element[i]; \
+ } else { \
+ result.element[n_elems - i*2 - (1+HI_IDX)] = b->element[n_elems - i - 1]; \
+ result.element[n_elems - i*2 - (1+LO_IDX)] = a->element[n_elems - i - 1]; \
+ } \
+ } \
+ *r = result; \
+ }
+#if defined(WORDS_BIGENDIAN)
+#define MRGHI 0
+#define MRGL0 1
+#else
+#define MRGHI 1
+#define MRGLO 0
+#endif
+#define VMRG(suffix, element) \
+ VMRG_DO(mrgl##suffix, element, MRGHI) \
+ VMRG_DO(mrgh##suffix, element, MRGLO)
+VMRG(b, u8)
+VMRG(h, u16)
+VMRG(w, u32)
+#undef VMRG_DO
+#undef VMRG
+#undef MRGHI
+#undef MRGLO
+
#undef VECTOR_FOR_INORDER_I
#undef HI_IDX
#undef LO_IDX
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 7ebdb21..13fccf3 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6205,6 +6205,12 @@ GEN_VXFORM(vavguw, 1, 18);
GEN_VXFORM(vavgsb, 1, 20);
GEN_VXFORM(vavgsh, 1, 21);
GEN_VXFORM(vavgsw, 1, 22);
+GEN_VXFORM(vmrghb, 6, 0);
+GEN_VXFORM(vmrghh, 6, 1);
+GEN_VXFORM(vmrghw, 6, 2);
+GEN_VXFORM(vmrglb, 6, 4);
+GEN_VXFORM(vmrglh, 6, 5);
+GEN_VXFORM(vmrglw, 6, 6);
#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [PATCH 11/40] Add vmul{e,o}{s,u}{b,h} instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (9 preceding siblings ...)
2008-12-31 3:09 ` [Qemu-devel] [PATCH 10/40] Add vmrg{l,h}{b,h,w} instructions Nathan Froyd
@ 2008-12-31 3:09 ` Nathan Froyd
2008-12-31 3:09 ` [Qemu-devel] [PATCH 12/40] Add vsr{,a}{b,h,w} instructions Nathan Froyd
` (29 subsequent siblings)
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:09 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 8 ++++++++
target-ppc/op_helper.c | 22 ++++++++++++++++++++++
target-ppc/translate.c | 8 ++++++++
3 files changed, 38 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 5a05157..6b74c3d 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -138,6 +138,14 @@ DEF_HELPER_3(vcmpgtuw, i32, avr, avr, avr)
DEF_HELPER_3(vcmpgtsb, i32, avr, avr, avr)
DEF_HELPER_3(vcmpgtsh, i32, avr, avr, avr)
DEF_HELPER_3(vcmpgtsw, i32, avr, avr, avr)
+DEF_HELPER_3(vmulesb, void, avr, avr, avr)
+DEF_HELPER_3(vmulesh, void, avr, avr, avr)
+DEF_HELPER_3(vmuleub, void, avr, avr, avr)
+DEF_HELPER_3(vmuleuh, void, avr, avr, avr)
+DEF_HELPER_3(vmulosb, void, avr, avr, avr)
+DEF_HELPER_3(vmulosh, void, avr, avr, avr)
+DEF_HELPER_3(vmuloub, void, avr, avr, avr)
+DEF_HELPER_3(vmulouh, void, avr, avr, avr)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 0e502bc..ab8e15b 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2100,6 +2100,28 @@ VMRG(w, u32)
#undef MRGHI
#undef MRGLO
+#define VMUL_DO(name, mul_element, prod_element, evenp) \
+ void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+ { \
+ int i; \
+ VECTOR_FOR_INORDER_I(i, prod_element) { \
+ if (evenp) { \
+ r->prod_element[i] = a->mul_element[i*2+HI_IDX] * b->mul_element[i*2+HI_IDX]; \
+ } else { \
+ r->prod_element[i] = a->mul_element[i*2+LO_IDX] * b->mul_element[i*2+LO_IDX]; \
+ } \
+ } \
+ }
+#define VMUL(suffix, mul_element, prod_element) \
+ VMUL_DO(mule##suffix, mul_element, prod_element, 1) \
+ VMUL_DO(mulo##suffix, mul_element, prod_element, 0)
+VMUL(sb, s8, s16)
+VMUL(sh, s16, s32)
+VMUL(ub, u8, u16)
+VMUL(uh, u16, u32)
+#undef VMUL_DO
+#undef VMUL
+
#undef VECTOR_FOR_INORDER_I
#undef HI_IDX
#undef LO_IDX
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 13fccf3..741bbc9 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6211,6 +6211,14 @@ GEN_VXFORM(vmrghw, 6, 2);
GEN_VXFORM(vmrglb, 6, 4);
GEN_VXFORM(vmrglh, 6, 5);
GEN_VXFORM(vmrglw, 6, 6);
+GEN_VXFORM(vmuloub, 4, 0);
+GEN_VXFORM(vmulouh, 4, 1);
+GEN_VXFORM(vmulosb, 4, 4);
+GEN_VXFORM(vmulosh, 4, 5);
+GEN_VXFORM(vmuleub, 4, 8);
+GEN_VXFORM(vmuleuh, 4, 9);
+GEN_VXFORM(vmulesb, 4, 12);
+GEN_VXFORM(vmulesh, 4, 13);
#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [PATCH 12/40] Add vsr{,a}{b,h,w} instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (10 preceding siblings ...)
2008-12-31 3:09 ` [Qemu-devel] [PATCH 11/40] Add vmul{e,o}{s,u}{b,h} instructions Nathan Froyd
@ 2008-12-31 3:09 ` Nathan Froyd
2008-12-31 3:09 ` [Qemu-devel] [PATCH 13/40] Add vsl{b,h,w} instructions Nathan Froyd
` (28 subsequent siblings)
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:09 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 6 ++++++
target-ppc/op_helper.c | 18 ++++++++++++++++++
target-ppc/translate.c | 6 ++++++
3 files changed, 30 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 6b74c3d..f2e91ca 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -146,6 +146,12 @@ DEF_HELPER_3(vmulosb, void, avr, avr, avr)
DEF_HELPER_3(vmulosh, void, avr, avr, avr)
DEF_HELPER_3(vmuloub, void, avr, avr, avr)
DEF_HELPER_3(vmulouh, void, avr, avr, avr)
+DEF_HELPER_3(vsrab, void, avr, avr, avr)
+DEF_HELPER_3(vsrah, void, avr, avr, avr)
+DEF_HELPER_3(vsraw, void, avr, avr, avr)
+DEF_HELPER_3(vsrb, void, avr, avr, avr)
+DEF_HELPER_3(vsrh, void, avr, avr, avr)
+DEF_HELPER_3(vsrw, void, avr, avr, avr)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index ab8e15b..55f9c8b 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2122,6 +2122,24 @@ VMUL(uh, u16, u32)
#undef VMUL_DO
#undef VMUL
+#define VSR(suffix, element) \
+ void helper_vsr##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+ { \
+ int i; \
+ for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
+ unsigned int mask = ((1 << (3 + (sizeof (a->element[0]) >> 1))) - 1); \
+ unsigned int shift = b->element[i] & mask; \
+ r->element[i] = a->element[i] >> shift; \
+ } \
+ }
+VSR(ab, s8)
+VSR(ah, s16)
+VSR(aw, s32)
+VSR(b, u8)
+VSR(h, u16)
+VSR(w, u32)
+#undef VSR
+
#undef VECTOR_FOR_INORDER_I
#undef HI_IDX
#undef LO_IDX
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 741bbc9..246a8fd 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6219,6 +6219,12 @@ GEN_VXFORM(vmuleub, 4, 8);
GEN_VXFORM(vmuleuh, 4, 9);
GEN_VXFORM(vmulesb, 4, 12);
GEN_VXFORM(vmulesh, 4, 13);
+GEN_VXFORM(vsrb, 2, 8);
+GEN_VXFORM(vsrh, 2, 9);
+GEN_VXFORM(vsrw, 2, 10);
+GEN_VXFORM(vsrab, 2, 12);
+GEN_VXFORM(vsrah, 2, 13);
+GEN_VXFORM(vsraw, 2, 14);
#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [PATCH 13/40] Add vsl{b,h,w} instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (11 preceding siblings ...)
2008-12-31 3:09 ` [Qemu-devel] [PATCH 12/40] Add vsr{,a}{b,h,w} instructions Nathan Froyd
@ 2008-12-31 3:09 ` Nathan Froyd
2008-12-31 3:09 ` [Qemu-devel] [PATCH 14/40] Add vs{l,r}o instructions Nathan Froyd
` (27 subsequent siblings)
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:09 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 3 +++
target-ppc/op_helper.c | 15 +++++++++++++++
target-ppc/translate.c | 3 +++
3 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index f2e91ca..7f3b011 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -152,6 +152,9 @@ DEF_HELPER_3(vsraw, void, avr, avr, avr)
DEF_HELPER_3(vsrb, void, avr, avr, avr)
DEF_HELPER_3(vsrh, void, avr, avr, avr)
DEF_HELPER_3(vsrw, void, avr, avr, avr)
+DEF_HELPER_3(vslb, void, avr, avr, avr)
+DEF_HELPER_3(vslh, void, avr, avr, avr)
+DEF_HELPER_3(vslw, void, avr, avr, avr)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 55f9c8b..4addf9a 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2122,6 +2122,21 @@ VMUL(uh, u16, u32)
#undef VMUL_DO
#undef VMUL
+#define VSL(suffix, element) \
+ void helper_vsl##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+ { \
+ int i; \
+ for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
+ unsigned int mask = ((1 << (3 + (sizeof (a->element[0]) >> 1))) - 1); \
+ unsigned int shift = b->element[i] & mask; \
+ r->element[i] = a->element[i] << shift; \
+ } \
+ }
+VSL(b, u8)
+VSL(h, u16)
+VSL(w, u32)
+#undef VSL
+
#define VSR(suffix, element) \
void helper_vsr##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 246a8fd..ff3fcb1 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6219,6 +6219,9 @@ GEN_VXFORM(vmuleub, 4, 8);
GEN_VXFORM(vmuleuh, 4, 9);
GEN_VXFORM(vmulesb, 4, 12);
GEN_VXFORM(vmulesh, 4, 13);
+GEN_VXFORM(vslb, 2, 4);
+GEN_VXFORM(vslh, 2, 5);
+GEN_VXFORM(vslw, 2, 6);
GEN_VXFORM(vsrb, 2, 8);
GEN_VXFORM(vsrh, 2, 9);
GEN_VXFORM(vsrw, 2, 10);
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [PATCH 14/40] Add vs{l,r}o instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (12 preceding siblings ...)
2008-12-31 3:09 ` [Qemu-devel] [PATCH 13/40] Add vsl{b,h,w} instructions Nathan Froyd
@ 2008-12-31 3:09 ` Nathan Froyd
2008-12-31 3:09 ` [Qemu-devel] [PATCH 15/40] Add v{add,sub}cuw instructions Nathan Froyd
` (26 subsequent siblings)
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:09 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 2 ++
target-ppc/op_helper.c | 27 +++++++++++++++++++++++++++
target-ppc/translate.c | 2 ++
3 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 7f3b011..8f6f059 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -155,6 +155,8 @@ DEF_HELPER_3(vsrw, void, avr, avr, avr)
DEF_HELPER_3(vslb, void, avr, avr, avr)
DEF_HELPER_3(vslh, void, avr, avr, avr)
DEF_HELPER_3(vslw, void, avr, avr, avr)
+DEF_HELPER_3(vslo, void, avr, avr, avr)
+DEF_HELPER_3(vsro, void, avr, avr, avr)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 4addf9a..5451403 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -17,6 +17,7 @@
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
+#include <string.h>
#include "exec.h"
#include "host-utils.h"
#include "helper.h"
@@ -2137,6 +2138,19 @@ VSL(h, u16)
VSL(w, u32)
#undef VSL
+void helper_vslo (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ int sh = (b->u8[LO_IDX*0xf] >> 3) & 0xf;
+
+#if defined (WORDS_BIGENDIAN)
+ memmove (&r->u8[0], &a->u8[sh], 0x10-sh);
+ memset (&r->u8[16-sh], 0, sh);
+#else
+ memmove (&r->u8[sh], &a->u8[0], 0x10-sh);
+ memset (&r->u8[0], 0, sh);
+#endif
+}
+
#define VSR(suffix, element) \
void helper_vsr##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
@@ -2155,6 +2169,19 @@ VSR(h, u16)
VSR(w, u32)
#undef VSR
+void helper_vsro (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ int sh = (b->u8[LO_IDX*0xf] >> 3) & 0xf;
+
+#if defined (WORDS_BIGENDIAN)
+ memmove (&r->u8[sh], &a->u8[0], 0x10-sh);
+ memset (&r->u8[0], 0, sh);
+#else
+ memmove (&r->u8[0], &a->u8[sh], 0x10-sh);
+ memset (&r->u8[0x10-sh], 0, sh);
+#endif
+}
+
#undef VECTOR_FOR_INORDER_I
#undef HI_IDX
#undef LO_IDX
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index ff3fcb1..2c4b29a 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6228,6 +6228,8 @@ GEN_VXFORM(vsrw, 2, 10);
GEN_VXFORM(vsrab, 2, 12);
GEN_VXFORM(vsrah, 2, 13);
GEN_VXFORM(vsraw, 2, 14);
+GEN_VXFORM(vslo, 6, 16);
+GEN_VXFORM(vsro, 6, 17);
#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [PATCH 15/40] Add v{add,sub}cuw instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (13 preceding siblings ...)
2008-12-31 3:09 ` [Qemu-devel] [PATCH 14/40] Add vs{l,r}o instructions Nathan Froyd
@ 2008-12-31 3:09 ` Nathan Froyd
2008-12-31 3:09 ` [Qemu-devel] [PATCH 16/40] Add lvs{l,r} instructions Nathan Froyd
` (25 subsequent siblings)
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:09 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 2 ++
target-ppc/op_helper.c | 16 ++++++++++++++++
target-ppc/translate.c | 2 ++
3 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 8f6f059..a784fae 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -157,6 +157,8 @@ DEF_HELPER_3(vslh, void, avr, avr, avr)
DEF_HELPER_3(vslw, void, avr, avr, avr)
DEF_HELPER_3(vslo, void, avr, avr, avr)
DEF_HELPER_3(vsro, void, avr, avr, avr)
+DEF_HELPER_3(vaddcuw, void, avr, avr, avr)
+DEF_HELPER_3(vsubcuw, void, avr, avr, avr)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 5451403..b671247 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -1972,6 +1972,14 @@ target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_
for (index = ARRAY_SIZE(r->element)-1; index >= 0; index--)
#endif
+void helper_vaddcuw (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(r->u32); i++) {
+ r->u32[i] = ~a->u32[i] < b->u32[i];
+ }
+}
+
#define VARITH_DO(name, op, element) \
void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
@@ -2182,6 +2190,14 @@ void helper_vsro (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
#endif
}
+void helper_vsubcuw (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(r->u32); i++) {
+ r->u32[i] = a->u32[i] >= b->u32[i];
+ }
+}
+
#undef VECTOR_FOR_INORDER_I
#undef HI_IDX
#undef LO_IDX
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 2c4b29a..8dbe14a 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6230,6 +6230,8 @@ GEN_VXFORM(vsrah, 2, 13);
GEN_VXFORM(vsraw, 2, 14);
GEN_VXFORM(vslo, 6, 16);
GEN_VXFORM(vsro, 6, 17);
+GEN_VXFORM(vaddcuw, 0, 6);
+GEN_VXFORM(vsubcuw, 0, 22);
#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [PATCH 16/40] Add lvs{l,r} instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (14 preceding siblings ...)
2008-12-31 3:09 ` [Qemu-devel] [PATCH 15/40] Add v{add,sub}cuw instructions Nathan Froyd
@ 2008-12-31 3:09 ` Nathan Froyd
2008-12-31 3:09 ` [Qemu-devel] [PATCH 17/40] Add m{f,t}vscr instructions Nathan Froyd
` (24 subsequent siblings)
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:09 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 2 ++
target-ppc/op_helper.c | 18 ++++++++++++++++++
target-ppc/translate.c | 32 ++++++++++++++++++++++++++++++++
3 files changed, 52 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index a784fae..1d05cb2 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -159,6 +159,8 @@ DEF_HELPER_3(vslo, void, avr, avr, avr)
DEF_HELPER_3(vsro, void, avr, avr, avr)
DEF_HELPER_3(vaddcuw, void, avr, avr, avr)
DEF_HELPER_3(vsubcuw, void, avr, avr, avr)
+DEF_HELPER_2(lvsl, void, avr, tl);
+DEF_HELPER_2(lvsr, void, avr, tl);
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index b671247..0b44e7c 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -1972,6 +1972,24 @@ target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_
for (index = ARRAY_SIZE(r->element)-1; index >= 0; index--)
#endif
+void helper_lvsl (ppc_avr_t *r, target_ulong sh)
+{
+ int i, j = (sh & 0xf);
+
+ VECTOR_FOR_INORDER_I (i, u8) {
+ r->u8[i] = j++;
+ }
+}
+
+void helper_lvsr (ppc_avr_t *r, target_ulong sh)
+{
+ int i, j = 0x10 - (sh & 0xf);
+
+ VECTOR_FOR_INORDER_I (i, u8) {
+ r->u8[i] = j++;
+ }
+}
+
void helper_vaddcuw (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
{
int i;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 8dbe14a..4e1bd23 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6146,6 +6146,38 @@ GEN_VR_STX(svx, 0x07, 0x07);
/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
GEN_VR_STX(svxl, 0x07, 0x0F);
+GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC)
+{
+ TCGv_ptr rd;
+ TCGv EA;
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+ EA = tcg_temp_new();
+ gen_addr_reg_index(ctx, EA);
+ rd = gen_avr_ptr(rD(ctx->opcode));
+ gen_helper_lvsl(rd, EA);
+ tcg_temp_free(EA);
+ tcg_temp_free_ptr(rd);
+}
+
+GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC)
+{
+ TCGv_ptr rd;
+ TCGv EA;
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+ EA = tcg_temp_new();
+ gen_addr_reg_index(ctx, EA);
+ rd = gen_avr_ptr(rD(ctx->opcode));
+ gen_helper_lvsr(rd, EA);
+ tcg_temp_free(EA);
+ tcg_temp_free_ptr(rd);
+}
+
/* Logical operations */
#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [PATCH 17/40] Add m{f,t}vscr instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (15 preceding siblings ...)
2008-12-31 3:09 ` [Qemu-devel] [PATCH 16/40] Add lvs{l,r} instructions Nathan Froyd
@ 2008-12-31 3:09 ` Nathan Froyd
2009-01-03 19:43 ` Aurelien Jarno
2008-12-31 3:10 ` [Qemu-devel] [PATCH 18/40] Add v{add, sub}{s, u}{b, h, w}s instructions Nathan Froyd
` (23 subsequent siblings)
40 siblings, 1 reply; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:09 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/translate.c | 37 +++++++++++++++++++++++++++++++++++++
1 files changed, 37 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 4e1bd23..5c13ed2 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6178,6 +6178,43 @@ GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC)
tcg_temp_free_ptr(rd);
}
+static always_inline uint32_t gen_vscr_offset (int r)
+{
+#if defined(WORDS_BIGENDIAN)
+ return offsetof(CPUPPCState, avr[r].u32[3]);
+#else
+ return offsetof(CPUPPCState, avr[r].u32[0]);
+#endif
+}
+
+GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC)
+{
+ TCGv_i32 t;
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+ tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
+ tcg_gen_movi_i64(cpu_avrl[rD(ctx->opcode)], 0);
+ t = tcg_temp_new_i32();
+ tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr));
+ tcg_gen_st_i32(t, cpu_env, gen_vscr_offset(rD(ctx->opcode)));
+ tcg_temp_free_i32(t);
+}
+
+GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC)
+{
+ TCGv_i32 t;
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+ t = tcg_temp_new_i32();
+ tcg_gen_ld_i32(t, cpu_env, gen_vscr_offset(rB(ctx->opcode)));
+ tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, vscr));
+ tcg_temp_free_i32(t);
+}
+
/* Logical operations */
#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH 17/40] Add m{f,t}vscr instructions.
2008-12-31 3:09 ` [Qemu-devel] [PATCH 17/40] Add m{f,t}vscr instructions Nathan Froyd
@ 2009-01-03 19:43 ` Aurelien Jarno
0 siblings, 0 replies; 68+ messages in thread
From: Aurelien Jarno @ 2009-01-03 19:43 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Tue, Dec 30, 2008 at 07:09:59PM -0800, Nathan Froyd wrote:
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/translate.c | 37 +++++++++++++++++++++++++++++++++++++
> 1 files changed, 37 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 4e1bd23..5c13ed2 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6178,6 +6178,43 @@ GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC)
> tcg_temp_free_ptr(rd);
> }
>
> +static always_inline uint32_t gen_vscr_offset (int r)
> +{
> +#if defined(WORDS_BIGENDIAN)
> + return offsetof(CPUPPCState, avr[r].u32[3]);
> +#else
> + return offsetof(CPUPPCState, avr[r].u32[0]);
> +#endif
> +}
> +
> +GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC)
> +{
> + TCGv_i32 t;
> + if (unlikely(!ctx->altivec_enabled)) {
> + gen_exception(ctx, POWERPC_EXCP_VPU);
> + return;
> + }
> + tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
> + tcg_gen_movi_i64(cpu_avrl[rD(ctx->opcode)], 0);
> + t = tcg_temp_new_i32();
> + tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr));
> + tcg_gen_st_i32(t, cpu_env, gen_vscr_offset(rD(ctx->opcode)));
> + tcg_temp_free_i32(t);
> +}
TCG doesn't like when a variable is accessed through both a TCG register
and a TCG load/store in the same TB. This is most probably the problem
you are seeing with mfvscr/mtvscr.
I suggest you to replace the movi_i64 to cpu_avrl and the st_i32 by a
extu_i32_i64 to cpu_avrl.
> +GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC)
> +{
> + TCGv_i32 t;
> + if (unlikely(!ctx->altivec_enabled)) {
> + gen_exception(ctx, POWERPC_EXCP_VPU);
> + return;
> + }
> + t = tcg_temp_new_i32();
> + tcg_gen_ld_i32(t, cpu_env, gen_vscr_offset(rB(ctx->opcode)));
> + tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, vscr));
> + tcg_temp_free_i32(t);
> +}
The same way, the ld_i32 can be replaced by a trunc_i64_i32 on cpu_avrl.
This way you can get rid of gen_vscr_offset().
> /* Logical operations */
> #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
> GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 18/40] Add v{add, sub}{s, u}{b, h, w}s instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (16 preceding siblings ...)
2008-12-31 3:09 ` [Qemu-devel] [PATCH 17/40] Add m{f,t}vscr instructions Nathan Froyd
@ 2008-12-31 3:10 ` Nathan Froyd
2009-01-03 21:13 ` Aurelien Jarno
2008-12-31 3:10 ` [Qemu-devel] [PATCH 19/40] Add vrl{b,h,w} instructions Nathan Froyd
` (22 subsequent siblings)
40 siblings, 1 reply; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:10 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 12 ++++++++++++
target-ppc/op_helper.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++
target-ppc/translate.c | 12 ++++++++++++
3 files changed, 70 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 1d05cb2..4e1c307 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -161,6 +161,18 @@ DEF_HELPER_3(vaddcuw, void, avr, avr, avr)
DEF_HELPER_3(vsubcuw, void, avr, avr, avr)
DEF_HELPER_2(lvsl, void, avr, tl);
DEF_HELPER_2(lvsr, void, avr, tl);
+DEF_HELPER_3(vaddsbs, void, avr, avr, avr)
+DEF_HELPER_3(vaddshs, void, avr, avr, avr)
+DEF_HELPER_3(vaddsws, void, avr, avr, avr)
+DEF_HELPER_3(vsubsbs, void, avr, avr, avr)
+DEF_HELPER_3(vsubshs, void, avr, avr, avr)
+DEF_HELPER_3(vsubsws, void, avr, avr, avr)
+DEF_HELPER_3(vaddubs, void, avr, avr, avr)
+DEF_HELPER_3(vadduhs, void, avr, avr, avr)
+DEF_HELPER_3(vadduws, void, avr, avr, avr)
+DEF_HELPER_3(vsububs, void, avr, avr, avr)
+DEF_HELPER_3(vsubuhs, void, avr, avr, avr)
+DEF_HELPER_3(vsubuws, void, avr, avr, avr)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 0b44e7c..1468656 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2015,6 +2015,52 @@ VARITH(uwm, u32)
#undef VARITH_DO
#undef VARITH
+#define VARITHSAT_CASE(type, op, min, max, use_min, use_max, element) \
+ { \
+ type result = (type)a->element[i] op (type)b->element[i]; \
+ if (use_min && result < min) { \
+ result = min; \
+ sat = 1; \
+ } else if (use_max && result > max) { \
+ result = max; \
+ sat = 1; \
+ } \
+ r->element[i] = result; \
+ }
+
+#define VARITHSAT_DO(name, op, min, max, use_min, use_max, element) \
+ void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+ { \
+ int sat = 0; \
+ int i; \
+ for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
+ switch (sizeof(r->element[0])) { \
+ case 1: VARITHSAT_CASE(int16_t, op, min, max, use_min, use_max, element); break; \
+ case 2: VARITHSAT_CASE(int32_t, op, min, max, use_min, use_max, element); break; \
+ case 4: VARITHSAT_CASE(int64_t, op, min, max, use_min, use_max, element); break; \
+ } \
+ } \
+ if (sat) { \
+ env->vscr |= (1 << VSCR_SAT); \
+ } \
+ }
+#define VARITHSAT_SIGNED(suffix, element, min, max) \
+ VARITHSAT_DO(adds##suffix##s, +, min, max, 1, 1, element) \
+ VARITHSAT_DO(subs##suffix##s, -, min, max, 1, 1, element)
+#define VARITHSAT_UNSIGNED(suffix, element, max) \
+ VARITHSAT_DO(addu##suffix##s, +, 0, max, 0, 1, element) \
+ VARITHSAT_DO(subu##suffix##s, -, 0, max, 1, 0, element)
+VARITHSAT_SIGNED(b, s8, INT8_MIN, INT8_MAX)
+VARITHSAT_SIGNED(h, s16, INT16_MIN, INT16_MAX)
+VARITHSAT_SIGNED(w, s32, INT32_MIN, INT32_MAX)
+VARITHSAT_UNSIGNED(b, u8, UINT8_MAX)
+VARITHSAT_UNSIGNED(h, u16, UINT16_MAX)
+VARITHSAT_UNSIGNED(w, u32, UINT32_MAX)
+#undef VARITHSAT_CASE
+#undef VARITHSAT_DO
+#undef VARITHSAT_SIGNED
+#undef VARITHSAT_UNSIGNED
+
#define VAVG_DO(name, element, etype) \
void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 5c13ed2..7a6c6e4 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6301,6 +6301,18 @@ GEN_VXFORM(vslo, 6, 16);
GEN_VXFORM(vsro, 6, 17);
GEN_VXFORM(vaddcuw, 0, 6);
GEN_VXFORM(vsubcuw, 0, 22);
+GEN_VXFORM(vaddubs, 0, 8);
+GEN_VXFORM(vadduhs, 0, 9);
+GEN_VXFORM(vadduws, 0, 10);
+GEN_VXFORM(vaddsbs, 0, 12);
+GEN_VXFORM(vaddshs, 0, 13);
+GEN_VXFORM(vaddsws, 0, 14);
+GEN_VXFORM(vsububs, 0, 24);
+GEN_VXFORM(vsubuhs, 0, 25);
+GEN_VXFORM(vsubuws, 0, 26);
+GEN_VXFORM(vsubsbs, 0, 28);
+GEN_VXFORM(vsubshs, 0, 29);
+GEN_VXFORM(vsubsws, 0, 30);
#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH 18/40] Add v{add, sub}{s, u}{b, h, w}s instructions.
2008-12-31 3:10 ` [Qemu-devel] [PATCH 18/40] Add v{add, sub}{s, u}{b, h, w}s instructions Nathan Froyd
@ 2009-01-03 21:13 ` Aurelien Jarno
2009-01-07 21:24 ` Nathan Froyd
0 siblings, 1 reply; 68+ messages in thread
From: Aurelien Jarno @ 2009-01-03 21:13 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Tue, Dec 30, 2008 at 07:10:00PM -0800, Nathan Froyd wrote:
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/helper.h | 12 ++++++++++++
> target-ppc/op_helper.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++
> target-ppc/translate.c | 12 ++++++++++++
> 3 files changed, 70 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 1d05cb2..4e1c307 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -161,6 +161,18 @@ DEF_HELPER_3(vaddcuw, void, avr, avr, avr)
> DEF_HELPER_3(vsubcuw, void, avr, avr, avr)
> DEF_HELPER_2(lvsl, void, avr, tl);
> DEF_HELPER_2(lvsr, void, avr, tl);
> +DEF_HELPER_3(vaddsbs, void, avr, avr, avr)
> +DEF_HELPER_3(vaddshs, void, avr, avr, avr)
> +DEF_HELPER_3(vaddsws, void, avr, avr, avr)
> +DEF_HELPER_3(vsubsbs, void, avr, avr, avr)
> +DEF_HELPER_3(vsubshs, void, avr, avr, avr)
> +DEF_HELPER_3(vsubsws, void, avr, avr, avr)
> +DEF_HELPER_3(vaddubs, void, avr, avr, avr)
> +DEF_HELPER_3(vadduhs, void, avr, avr, avr)
> +DEF_HELPER_3(vadduws, void, avr, avr, avr)
> +DEF_HELPER_3(vsububs, void, avr, avr, avr)
> +DEF_HELPER_3(vsubuhs, void, avr, avr, avr)
> +DEF_HELPER_3(vsubuws, void, avr, avr, avr)
>
> DEF_HELPER_1(efscfsi, i32, i32)
> DEF_HELPER_1(efscfui, i32, i32)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index 0b44e7c..1468656 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2015,6 +2015,52 @@ VARITH(uwm, u32)
> #undef VARITH_DO
> #undef VARITH
>
> +#define VARITHSAT_CASE(type, op, min, max, use_min, use_max, element) \
> + { \
> + type result = (type)a->element[i] op (type)b->element[i]; \
> + if (use_min && result < min) { \
> + result = min; \
> + sat = 1; \
> + } else if (use_max && result > max) { \
> + result = max; \
> + sat = 1; \
> + } \
> + r->element[i] = result; \
> + }
> +
> +#define VARITHSAT_DO(name, op, min, max, use_min, use_max, element) \
> + void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> + { \
> + int sat = 0; \
> + int i; \
> + for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
> + switch (sizeof(r->element[0])) { \
> + case 1: VARITHSAT_CASE(int16_t, op, min, max, use_min, use_max, element); break; \
> + case 2: VARITHSAT_CASE(int32_t, op, min, max, use_min, use_max, element); break; \
> + case 4: VARITHSAT_CASE(int64_t, op, min, max, use_min, use_max, element); break; \
> + } \
> + } \
> + if (sat) { \
> + env->vscr |= (1 << VSCR_SAT); \
> + } \
> + }
> +#define VARITHSAT_SIGNED(suffix, element, min, max) \
> + VARITHSAT_DO(adds##suffix##s, +, min, max, 1, 1, element) \
> + VARITHSAT_DO(subs##suffix##s, -, min, max, 1, 1, element)
> +#define VARITHSAT_UNSIGNED(suffix, element, max) \
> + VARITHSAT_DO(addu##suffix##s, +, 0, max, 0, 1, element) \
> + VARITHSAT_DO(subu##suffix##s, -, 0, max, 1, 0, element)
> +VARITHSAT_SIGNED(b, s8, INT8_MIN, INT8_MAX)
> +VARITHSAT_SIGNED(h, s16, INT16_MIN, INT16_MAX)
> +VARITHSAT_SIGNED(w, s32, INT32_MIN, INT32_MAX)
> +VARITHSAT_UNSIGNED(b, u8, UINT8_MAX)
> +VARITHSAT_UNSIGNED(h, u16, UINT16_MAX)
> +VARITHSAT_UNSIGNED(w, u32, UINT32_MAX)
> +#undef VARITHSAT_CASE
> +#undef VARITHSAT_DO
> +#undef VARITHSAT_SIGNED
> +#undef VARITHSAT_UNSIGNED
> +
> #define VAVG_DO(name, element, etype) \
> void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> { \
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 5c13ed2..7a6c6e4 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6301,6 +6301,18 @@ GEN_VXFORM(vslo, 6, 16);
> GEN_VXFORM(vsro, 6, 17);
> GEN_VXFORM(vaddcuw, 0, 6);
> GEN_VXFORM(vsubcuw, 0, 22);
> +GEN_VXFORM(vaddubs, 0, 8);
> +GEN_VXFORM(vadduhs, 0, 9);
> +GEN_VXFORM(vadduws, 0, 10);
> +GEN_VXFORM(vaddsbs, 0, 12);
> +GEN_VXFORM(vaddshs, 0, 13);
> +GEN_VXFORM(vaddsws, 0, 14);
> +GEN_VXFORM(vsububs, 0, 24);
> +GEN_VXFORM(vsubuhs, 0, 25);
> +GEN_VXFORM(vsubuws, 0, 26);
> +GEN_VXFORM(vsubsbs, 0, 28);
> +GEN_VXFORM(vsubshs, 0, 29);
> +GEN_VXFORM(vsubsws, 0, 30);
>
> #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
> GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
This patch introduces some new warnings:
/home/aurel32/git/qemu/target-ppc/op_helper.c: In function ‘helper_vaddsws’:
/home/aurel32/git/qemu/target-ppc/op_helper.c:2122: warning: overflow in implicit constant conversion
/home/aurel32/git/qemu/target-ppc/op_helper.c:2122: warning: overflow in implicit constant conversion
/home/aurel32/git/qemu/target-ppc/op_helper.c: In function ‘helper_vsubsws’:
/home/aurel32/git/qemu/target-ppc/op_helper.c:2122: warning: overflow in implicit constant conversion
/home/aurel32/git/qemu/target-ppc/op_helper.c:2122: warning: overflow in implicit constant conversion
/home/aurel32/git/qemu/target-ppc/op_helper.c: In function ‘helper_vadduws’:
/home/aurel32/git/qemu/target-ppc/op_helper.c:2125: warning: overflow in implicit constant conversion
/home/aurel32/git/qemu/target-ppc/op_helper.c: In function ‘helper_vsubuws’:
/home/aurel32/git/qemu/target-ppc/op_helper.c:2125: warning: overflow in implicit constant conversion
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH 18/40] Add v{add, sub}{s, u}{b, h, w}s instructions.
2009-01-03 21:13 ` Aurelien Jarno
@ 2009-01-07 21:24 ` Nathan Froyd
2009-01-08 23:19 ` Aurelien Jarno
0 siblings, 1 reply; 68+ messages in thread
From: Nathan Froyd @ 2009-01-07 21:24 UTC (permalink / raw)
To: qemu-devel
On Sat, Jan 03, 2009 at 10:13:20PM +0100, Aurelien Jarno wrote:
> This patch introduces some new warnings:
> /home/aurel32/git/qemu/target-ppc/op_helper.c: In function ‘helper_vaddsws’:
> /home/aurel32/git/qemu/target-ppc/op_helper.c:2122: warning: overflow in implicit constant conversion
> /home/aurel32/git/qemu/target-ppc/op_helper.c:2122: warning: overflow in implicit constant conversion
> /home/aurel32/git/qemu/target-ppc/op_helper.c: In function ‘helper_vsubsws’:
> /home/aurel32/git/qemu/target-ppc/op_helper.c:2122: warning: overflow in implicit constant conversion
> /home/aurel32/git/qemu/target-ppc/op_helper.c:2122: warning: overflow in implicit constant conversion
> /home/aurel32/git/qemu/target-ppc/op_helper.c: In function ‘helper_vadduws’:
> /home/aurel32/git/qemu/target-ppc/op_helper.c:2125: warning: overflow in implicit constant conversion
> /home/aurel32/git/qemu/target-ppc/op_helper.c: In function ‘helper_vsubuws’:
> /home/aurel32/git/qemu/target-ppc/op_helper.c:2125: warning: overflow in implicit constant conversion
Fixed thusly. (I still get a warning for cvtuhub, which can be fixed
separately.)
-Nathan
Fix compilation warnings by using the cvt* family of functions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 12 ++++++++++++
target-ppc/op_helper.c | 39 +++++++++++++++++++++++++++++++++++++++
target-ppc/translate.c | 12 ++++++++++++
3 files changed, 63 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index bae137b..009f516 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -170,6 +170,18 @@ DEF_HELPER_3(vaddcuw, void, avr, avr, avr)
DEF_HELPER_3(vsubcuw, void, avr, avr, avr)
DEF_HELPER_2(lvsl, void, avr, tl);
DEF_HELPER_2(lvsr, void, avr, tl);
+DEF_HELPER_3(vaddsbs, void, avr, avr, avr)
+DEF_HELPER_3(vaddshs, void, avr, avr, avr)
+DEF_HELPER_3(vaddsws, void, avr, avr, avr)
+DEF_HELPER_3(vsubsbs, void, avr, avr, avr)
+DEF_HELPER_3(vsubshs, void, avr, avr, avr)
+DEF_HELPER_3(vsubsws, void, avr, avr, avr)
+DEF_HELPER_3(vaddubs, void, avr, avr, avr)
+DEF_HELPER_3(vadduhs, void, avr, avr, avr)
+DEF_HELPER_3(vadduws, void, avr, avr, avr)
+DEF_HELPER_3(vsububs, void, avr, avr, avr)
+DEF_HELPER_3(vsubuhs, void, avr, avr, avr)
+DEF_HELPER_3(vsubuws, void, avr, avr, avr)
DEF_HELPER_3(vrlb, void, avr, avr, avr)
DEF_HELPER_3(vrlh, void, avr, avr, avr)
DEF_HELPER_3(vrlw, void, avr, avr, avr)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index eb155aa..ef19bde 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2082,6 +2082,45 @@ VARITH(uwm, u32)
#undef VARITH_DO
#undef VARITH
+#define VARITHSAT_CASE(type, op, cvt, element) \
+ { \
+ type result = (type)a->element[i] op (type)b->element[i]; \
+ r->element[i] = cvt(result, &sat); \
+ }
+
+#define VARITHSAT_DO(name, op, optype, cvt, element) \
+ void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+ { \
+ int sat = 0; \
+ int i; \
+ for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
+ switch (sizeof(r->element[0])) { \
+ case 1: VARITHSAT_CASE(optype, op, cvt, element); break; \
+ case 2: VARITHSAT_CASE(optype, op, cvt, element); break; \
+ case 4: VARITHSAT_CASE(optype, op, cvt, element); break; \
+ } \
+ } \
+ if (sat) { \
+ env->vscr |= (1 << VSCR_SAT); \
+ } \
+ }
+#define VARITHSAT_SIGNED(suffix, element, optype, cvt) \
+ VARITHSAT_DO(adds##suffix##s, +, optype, cvt, element) \
+ VARITHSAT_DO(subs##suffix##s, -, optype, cvt, element)
+#define VARITHSAT_UNSIGNED(suffix, element, optype, cvt) \
+ VARITHSAT_DO(addu##suffix##s, +, optype, cvt, element) \
+ VARITHSAT_DO(subu##suffix##s, -, optype, cvt, element)
+VARITHSAT_SIGNED(b, s8, int16_t, cvtshsb)
+VARITHSAT_SIGNED(h, s16, int32_t, cvtswsh)
+VARITHSAT_SIGNED(w, s32, int64_t, cvtsdsw)
+VARITHSAT_UNSIGNED(b, u8, uint16_t, cvtuhub)
+VARITHSAT_UNSIGNED(h, u16, uint32_t, cvtuwuh)
+VARITHSAT_UNSIGNED(w, u32, uint64_t, cvtuduw)
+#undef VARITHSAT_CASE
+#undef VARITHSAT_DO
+#undef VARITHSAT_SIGNED
+#undef VARITHSAT_UNSIGNED
+
#define VAVG_DO(name, element, etype) \
void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 20e9e0c..e92156f 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6341,6 +6341,18 @@ GEN_VXFORM(vslo, 6, 16);
GEN_VXFORM(vsro, 6, 17);
GEN_VXFORM(vaddcuw, 0, 6);
GEN_VXFORM(vsubcuw, 0, 22);
+GEN_VXFORM(vaddubs, 0, 8);
+GEN_VXFORM(vadduhs, 0, 9);
+GEN_VXFORM(vadduws, 0, 10);
+GEN_VXFORM(vaddsbs, 0, 12);
+GEN_VXFORM(vaddshs, 0, 13);
+GEN_VXFORM(vaddsws, 0, 14);
+GEN_VXFORM(vsububs, 0, 24);
+GEN_VXFORM(vsubuhs, 0, 25);
+GEN_VXFORM(vsubuws, 0, 26);
+GEN_VXFORM(vsubsbs, 0, 28);
+GEN_VXFORM(vsubshs, 0, 29);
+GEN_VXFORM(vsubsws, 0, 30);
GEN_VXFORM(vrlb, 2, 0);
GEN_VXFORM(vrlh, 2, 1);
GEN_VXFORM(vrlw, 2, 2);
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH 18/40] Add v{add, sub}{s, u}{b, h, w}s instructions.
2009-01-07 21:24 ` Nathan Froyd
@ 2009-01-08 23:19 ` Aurelien Jarno
0 siblings, 0 replies; 68+ messages in thread
From: Aurelien Jarno @ 2009-01-08 23:19 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Wed, Jan 07, 2009 at 01:24:30PM -0800, Nathan Froyd wrote:
> On Sat, Jan 03, 2009 at 10:13:20PM +0100, Aurelien Jarno wrote:
> > This patch introduces some new warnings:
> > /home/aurel32/git/qemu/target-ppc/op_helper.c: In function ‘helper_vaddsws’:
> > /home/aurel32/git/qemu/target-ppc/op_helper.c:2122: warning: overflow in implicit constant conversion
> > /home/aurel32/git/qemu/target-ppc/op_helper.c:2122: warning: overflow in implicit constant conversion
> > /home/aurel32/git/qemu/target-ppc/op_helper.c: In function ‘helper_vsubsws’:
> > /home/aurel32/git/qemu/target-ppc/op_helper.c:2122: warning: overflow in implicit constant conversion
> > /home/aurel32/git/qemu/target-ppc/op_helper.c:2122: warning: overflow in implicit constant conversion
> > /home/aurel32/git/qemu/target-ppc/op_helper.c: In function ‘helper_vadduws’:
> > /home/aurel32/git/qemu/target-ppc/op_helper.c:2125: warning: overflow in implicit constant conversion
> > /home/aurel32/git/qemu/target-ppc/op_helper.c: In function ‘helper_vsubuws’:
> > /home/aurel32/git/qemu/target-ppc/op_helper.c:2125: warning: overflow in implicit constant conversion
>
> Fixed thusly. (I still get a warning for cvtuhub, which can be fixed
> separately.)
>
> -Nathan
>
> Fix compilation warnings by using the cvt* family of functions.
Thanks, applied with minor fixes to pass the testsuite (use the signed
to unsigned conversion for unsigned instructions to correctly clamp the
value to 0 in case of a subtraction).
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/helper.h | 12 ++++++++++++
> target-ppc/op_helper.c | 39 +++++++++++++++++++++++++++++++++++++++
> target-ppc/translate.c | 12 ++++++++++++
> 3 files changed, 63 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index bae137b..009f516 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -170,6 +170,18 @@ DEF_HELPER_3(vaddcuw, void, avr, avr, avr)
> DEF_HELPER_3(vsubcuw, void, avr, avr, avr)
> DEF_HELPER_2(lvsl, void, avr, tl);
> DEF_HELPER_2(lvsr, void, avr, tl);
> +DEF_HELPER_3(vaddsbs, void, avr, avr, avr)
> +DEF_HELPER_3(vaddshs, void, avr, avr, avr)
> +DEF_HELPER_3(vaddsws, void, avr, avr, avr)
> +DEF_HELPER_3(vsubsbs, void, avr, avr, avr)
> +DEF_HELPER_3(vsubshs, void, avr, avr, avr)
> +DEF_HELPER_3(vsubsws, void, avr, avr, avr)
> +DEF_HELPER_3(vaddubs, void, avr, avr, avr)
> +DEF_HELPER_3(vadduhs, void, avr, avr, avr)
> +DEF_HELPER_3(vadduws, void, avr, avr, avr)
> +DEF_HELPER_3(vsububs, void, avr, avr, avr)
> +DEF_HELPER_3(vsubuhs, void, avr, avr, avr)
> +DEF_HELPER_3(vsubuws, void, avr, avr, avr)
> DEF_HELPER_3(vrlb, void, avr, avr, avr)
> DEF_HELPER_3(vrlh, void, avr, avr, avr)
> DEF_HELPER_3(vrlw, void, avr, avr, avr)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index eb155aa..ef19bde 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2082,6 +2082,45 @@ VARITH(uwm, u32)
> #undef VARITH_DO
> #undef VARITH
>
> +#define VARITHSAT_CASE(type, op, cvt, element) \
> + { \
> + type result = (type)a->element[i] op (type)b->element[i]; \
> + r->element[i] = cvt(result, &sat); \
> + }
> +
> +#define VARITHSAT_DO(name, op, optype, cvt, element) \
> + void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> + { \
> + int sat = 0; \
> + int i; \
> + for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
> + switch (sizeof(r->element[0])) { \
> + case 1: VARITHSAT_CASE(optype, op, cvt, element); break; \
> + case 2: VARITHSAT_CASE(optype, op, cvt, element); break; \
> + case 4: VARITHSAT_CASE(optype, op, cvt, element); break; \
> + } \
> + } \
> + if (sat) { \
> + env->vscr |= (1 << VSCR_SAT); \
> + } \
> + }
> +#define VARITHSAT_SIGNED(suffix, element, optype, cvt) \
> + VARITHSAT_DO(adds##suffix##s, +, optype, cvt, element) \
> + VARITHSAT_DO(subs##suffix##s, -, optype, cvt, element)
> +#define VARITHSAT_UNSIGNED(suffix, element, optype, cvt) \
> + VARITHSAT_DO(addu##suffix##s, +, optype, cvt, element) \
> + VARITHSAT_DO(subu##suffix##s, -, optype, cvt, element)
> +VARITHSAT_SIGNED(b, s8, int16_t, cvtshsb)
> +VARITHSAT_SIGNED(h, s16, int32_t, cvtswsh)
> +VARITHSAT_SIGNED(w, s32, int64_t, cvtsdsw)
> +VARITHSAT_UNSIGNED(b, u8, uint16_t, cvtuhub)
> +VARITHSAT_UNSIGNED(h, u16, uint32_t, cvtuwuh)
> +VARITHSAT_UNSIGNED(w, u32, uint64_t, cvtuduw)
> +#undef VARITHSAT_CASE
> +#undef VARITHSAT_DO
> +#undef VARITHSAT_SIGNED
> +#undef VARITHSAT_UNSIGNED
> +
> #define VAVG_DO(name, element, etype) \
> void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> { \
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 20e9e0c..e92156f 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6341,6 +6341,18 @@ GEN_VXFORM(vslo, 6, 16);
> GEN_VXFORM(vsro, 6, 17);
> GEN_VXFORM(vaddcuw, 0, 6);
> GEN_VXFORM(vsubcuw, 0, 22);
> +GEN_VXFORM(vaddubs, 0, 8);
> +GEN_VXFORM(vadduhs, 0, 9);
> +GEN_VXFORM(vadduws, 0, 10);
> +GEN_VXFORM(vaddsbs, 0, 12);
> +GEN_VXFORM(vaddshs, 0, 13);
> +GEN_VXFORM(vaddsws, 0, 14);
> +GEN_VXFORM(vsububs, 0, 24);
> +GEN_VXFORM(vsubuhs, 0, 25);
> +GEN_VXFORM(vsubuws, 0, 26);
> +GEN_VXFORM(vsubsbs, 0, 28);
> +GEN_VXFORM(vsubshs, 0, 29);
> +GEN_VXFORM(vsubsws, 0, 30);
> GEN_VXFORM(vrlb, 2, 0);
> GEN_VXFORM(vrlh, 2, 1);
> GEN_VXFORM(vrlw, 2, 2);
> --
> 1.6.0.5
>
>
>
>
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 19/40] Add vrl{b,h,w} instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (17 preceding siblings ...)
2008-12-31 3:10 ` [Qemu-devel] [PATCH 18/40] Add v{add, sub}{s, u}{b, h, w}s instructions Nathan Froyd
@ 2008-12-31 3:10 ` Nathan Froyd
2008-12-31 3:10 ` [Qemu-devel] [PATCH 20/40] Add vs{l,r} instructions Nathan Froyd
` (21 subsequent siblings)
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:10 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 3 +++
target-ppc/op_helper.c | 15 +++++++++++++++
target-ppc/translate.c | 3 +++
3 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 4e1c307..cf2a655 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -173,6 +173,9 @@ DEF_HELPER_3(vadduws, void, avr, avr, avr)
DEF_HELPER_3(vsububs, void, avr, avr, avr)
DEF_HELPER_3(vsubuhs, void, avr, avr, avr)
DEF_HELPER_3(vsubuws, void, avr, avr, avr)
+DEF_HELPER_3(vrlb, void, avr, avr, avr)
+DEF_HELPER_3(vrlh, void, avr, avr, avr)
+DEF_HELPER_3(vrlw, void, avr, avr, avr)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 1468656..15eee72 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2195,6 +2195,21 @@ VMUL(uh, u16, u32)
#undef VMUL_DO
#undef VMUL
+#define VROTATE(suffix, element) \
+ void helper_vrl##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+ { \
+ int i; \
+ for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
+ unsigned int mask = ((1 << (3 + (sizeof (a->element[0]) >> 1))) - 1); \
+ unsigned int shift = b->element[i] & mask; \
+ r->element[i] = (a->element[i] << shift) | (a->element[i] >> (sizeof(a->element[0]) * 8 - shift)); \
+ } \
+ }
+VROTATE(b, u8)
+VROTATE(h, u16)
+VROTATE(w, u32)
+#undef VROTATE
+
#define VSL(suffix, element) \
void helper_vsl##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 7a6c6e4..a853683 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6313,6 +6313,9 @@ GEN_VXFORM(vsubuws, 0, 26);
GEN_VXFORM(vsubsbs, 0, 28);
GEN_VXFORM(vsubshs, 0, 29);
GEN_VXFORM(vsubsws, 0, 30);
+GEN_VXFORM(vrlb, 2, 0);
+GEN_VXFORM(vrlh, 2, 1);
+GEN_VXFORM(vrlw, 2, 2);
#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [PATCH 20/40] Add vs{l,r} instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (18 preceding siblings ...)
2008-12-31 3:10 ` [Qemu-devel] [PATCH 19/40] Add vrl{b,h,w} instructions Nathan Froyd
@ 2008-12-31 3:10 ` Nathan Froyd
2009-01-03 21:26 ` Aurelien Jarno
2008-12-31 3:10 ` [Qemu-devel] [PATCH 21/40] Add vsldoi instruction Nathan Froyd
` (20 subsequent siblings)
40 siblings, 1 reply; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:10 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 2 ++
target-ppc/op_helper.c | 36 ++++++++++++++++++++++++++++++++++++
target-ppc/translate.c | 2 ++
3 files changed, 40 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index cf2a655..5f94e9f 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -176,6 +176,8 @@ DEF_HELPER_3(vsubuws, void, avr, avr, avr)
DEF_HELPER_3(vrlb, void, avr, avr, avr)
DEF_HELPER_3(vrlh, void, avr, avr, avr)
DEF_HELPER_3(vrlw, void, avr, avr, avr)
+DEF_HELPER_3(vsl, void, avr, avr, avr)
+DEF_HELPER_3(vsr, void, avr, avr, avr)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 15eee72..ce47ef1 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2210,6 +2210,42 @@ VROTATE(h, u16)
VROTATE(w, u32)
#undef VROTATE
+#if defined(WORDS_BIGENDIAN)
+#define LEFT 0
+#define RIGHT 1
+#else
+#define LEFT 1
+#define RIGHT 0
+#endif
+#define VSHIFT(suffix, leftp) \
+ void helper_vs##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+ { \
+ int shift = b->u8[LO_IDX*0x15] & 0x7; \
+ int doit = 1; \
+ int i; \
+ for (i = 0; i < ARRAY_SIZE(r->u8); i++) { \
+ doit = doit && ((b->u8[i] & 0x7) == shift); \
+ } \
+ if (doit) { \
+ if (shift == 0) { \
+ *r = *a; \
+ } else if (leftp) { \
+ uint64_t carry = a->u64[LO_IDX] >> (64 - shift); \
+ r->u64[HI_IDX] = (a->u64[HI_IDX] << shift) | carry; \
+ r->u64[LO_IDX] = a->u64[LO_IDX] << shift; \
+ } else { \
+ uint64_t carry = a->u64[HI_IDX] << (64 - shift); \
+ r->u64[LO_IDX] = (a->u64[LO_IDX] >> shift) | carry; \
+ r->u64[HI_IDX] = a->u64[HI_IDX] >> shift; \
+ } \
+ } \
+ }
+VSHIFT(l, LEFT)
+VSHIFT(r, RIGHT)
+#undef VSHIFT
+#undef LEFT
+#undef RIGHT
+
#define VSL(suffix, element) \
void helper_vsl##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index a853683..b50aba3 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6316,6 +6316,8 @@ GEN_VXFORM(vsubsws, 0, 30);
GEN_VXFORM(vrlb, 2, 0);
GEN_VXFORM(vrlh, 2, 1);
GEN_VXFORM(vrlw, 2, 2);
+GEN_VXFORM(vsl, 2, 7);
+GEN_VXFORM(vsr, 2, 11);
#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH 20/40] Add vs{l,r} instructions.
2008-12-31 3:10 ` [Qemu-devel] [PATCH 20/40] Add vs{l,r} instructions Nathan Froyd
@ 2009-01-03 21:26 ` Aurelien Jarno
2009-01-05 18:29 ` Nathan Froyd
0 siblings, 1 reply; 68+ messages in thread
From: Aurelien Jarno @ 2009-01-03 21:26 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Tue, Dec 30, 2008 at 07:10:02PM -0800, Nathan Froyd wrote:
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/helper.h | 2 ++
> target-ppc/op_helper.c | 36 ++++++++++++++++++++++++++++++++++++
> target-ppc/translate.c | 2 ++
> 3 files changed, 40 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index cf2a655..5f94e9f 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -176,6 +176,8 @@ DEF_HELPER_3(vsubuws, void, avr, avr, avr)
> DEF_HELPER_3(vrlb, void, avr, avr, avr)
> DEF_HELPER_3(vrlh, void, avr, avr, avr)
> DEF_HELPER_3(vrlw, void, avr, avr, avr)
> +DEF_HELPER_3(vsl, void, avr, avr, avr)
> +DEF_HELPER_3(vsr, void, avr, avr, avr)
>
> DEF_HELPER_1(efscfsi, i32, i32)
> DEF_HELPER_1(efscfui, i32, i32)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index 15eee72..ce47ef1 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2210,6 +2210,42 @@ VROTATE(h, u16)
> VROTATE(w, u32)
> #undef VROTATE
>
> +#if defined(WORDS_BIGENDIAN)
> +#define LEFT 0
> +#define RIGHT 1
> +#else
> +#define LEFT 1
> +#define RIGHT 0
> +#endif
> +#define VSHIFT(suffix, leftp) \
> + void helper_vs##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> + { \
> + int shift = b->u8[LO_IDX*0x15] & 0x7; \
> + int doit = 1; \
> + int i; \
> + for (i = 0; i < ARRAY_SIZE(r->u8); i++) { \
> + doit = doit && ((b->u8[i] & 0x7) == shift); \
> + } \
According to the specification, the result is undefined in that case. I
think that always doing the computation is fine.
> + if (doit) { \
> + if (shift == 0) { \
> + *r = *a; \
> + } else if (leftp) { \
> + uint64_t carry = a->u64[LO_IDX] >> (64 - shift); \
> + r->u64[HI_IDX] = (a->u64[HI_IDX] << shift) | carry; \
> + r->u64[LO_IDX] = a->u64[LO_IDX] << shift; \
> + } else { \
> + uint64_t carry = a->u64[HI_IDX] << (64 - shift); \
> + r->u64[LO_IDX] = (a->u64[LO_IDX] >> shift) | carry; \
> + r->u64[HI_IDX] = a->u64[HI_IDX] >> shift; \
> + } \
> + } \
> + }
> +VSHIFT(l, LEFT)
> +VSHIFT(r, RIGHT)
> +#undef VSHIFT
> +#undef LEFT
> +#undef RIGHT
> +
> #define VSL(suffix, element) \
> void helper_vsl##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> { \
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index a853683..b50aba3 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6316,6 +6316,8 @@ GEN_VXFORM(vsubsws, 0, 30);
> GEN_VXFORM(vrlb, 2, 0);
> GEN_VXFORM(vrlh, 2, 1);
> GEN_VXFORM(vrlw, 2, 2);
> +GEN_VXFORM(vsl, 2, 7);
> +GEN_VXFORM(vsr, 2, 11);
>
> #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
> GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
> --
> 1.6.0.5
>
>
>
>
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH 20/40] Add vs{l,r} instructions.
2009-01-03 21:26 ` Aurelien Jarno
@ 2009-01-05 18:29 ` Nathan Froyd
2009-01-05 19:27 ` Aurelien Jarno
0 siblings, 1 reply; 68+ messages in thread
From: Nathan Froyd @ 2009-01-05 18:29 UTC (permalink / raw)
To: qemu-devel
On Sat, Jan 03, 2009 at 10:26:55PM +0100, Aurelien Jarno wrote:
> On Tue, Dec 30, 2008 at 07:10:02PM -0800, Nathan Froyd wrote:
> > +#define VSHIFT(suffix, leftp) \
> > + void helper_vs##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> > + { \
> > + int shift = b->u8[LO_IDX*0x15] & 0x7; \
> > + int doit = 1; \
> > + int i; \
> > + for (i = 0; i < ARRAY_SIZE(r->u8); i++) { \
> > + doit = doit && ((b->u8[i] & 0x7) == shift); \
> > + } \
>
> According to the specification, the result is undefined in that case. I
> think that always doing the computation is fine.
FWIW, doing the check has the nice property of delivering the same
results as real hardware. If you're using a comparison program like
ppctester, reducing those spurious failures is a win. (There's already
spurious failures for div instructions in corner cases.)
-Nathan
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH 20/40] Add vs{l,r} instructions.
2009-01-05 18:29 ` Nathan Froyd
@ 2009-01-05 19:27 ` Aurelien Jarno
2009-01-07 21:25 ` Nathan Froyd
0 siblings, 1 reply; 68+ messages in thread
From: Aurelien Jarno @ 2009-01-05 19:27 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Mon, Jan 05, 2009 at 10:29:56AM -0800, Nathan Froyd wrote:
> On Sat, Jan 03, 2009 at 10:26:55PM +0100, Aurelien Jarno wrote:
> > On Tue, Dec 30, 2008 at 07:10:02PM -0800, Nathan Froyd wrote:
> > > +#define VSHIFT(suffix, leftp) \
> > > + void helper_vs##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> > > + { \
> > > + int shift = b->u8[LO_IDX*0x15] & 0x7; \
> > > + int doit = 1; \
> > > + int i; \
> > > + for (i = 0; i < ARRAY_SIZE(r->u8); i++) { \
> > > + doit = doit && ((b->u8[i] & 0x7) == shift); \
> > > + } \
> >
> > According to the specification, the result is undefined in that case. I
> > think that always doing the computation is fine.
>
> FWIW, doing the check has the nice property of delivering the same
> results as real hardware. If you're using a comparison program like
> ppctester, reducing those spurious failures is a win. (There's already
> spurious failures for div instructions in corner cases.)
Then I am fine with that. Could you please just add a comment that it is
not necessary according to the spec, but done to match real hardware?
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH 20/40] Add vs{l,r} instructions.
2009-01-05 19:27 ` Aurelien Jarno
@ 2009-01-07 21:25 ` Nathan Froyd
2009-01-08 18:56 ` Aurelien Jarno
0 siblings, 1 reply; 68+ messages in thread
From: Nathan Froyd @ 2009-01-07 21:25 UTC (permalink / raw)
To: qemu-devel
On Mon, Jan 05, 2009 at 08:27:30PM +0100, Aurelien Jarno wrote:
> On Mon, Jan 05, 2009 at 10:29:56AM -0800, Nathan Froyd wrote:
> > FWIW, doing the check has the nice property of delivering the same
> > results as real hardware. If you're using a comparison program like
> > ppctester, reducing those spurious failures is a win. (There's already
> > spurious failures for div instructions in corner cases.)
>
> Then I am fine with that. Could you please just add a comment that it is
> not necessary according to the spec, but done to match real hardware?
Done thusly.
-Nathan
>From aa19aa5e31aa9eec36a2cdfb2e1ed806555eda96 Mon Sep 17 00:00:00 2001
From: Nathan Froyd <froydnj@codesourcery.com>
Date: Thu, 11 Dec 2008 12:02:03 -0800
Subject: [PATCH 4/5] Add vs{l,r} instructions.
Add explanatory comment about why we check equality of shift counts.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 2 ++
target-ppc/op_helper.c | 39 +++++++++++++++++++++++++++++++++++++++
target-ppc/translate.c | 2 ++
3 files changed, 43 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 009f516..e15d6b0 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -185,6 +185,8 @@ DEF_HELPER_3(vsubuws, void, avr, avr, avr)
DEF_HELPER_3(vrlb, void, avr, avr, avr)
DEF_HELPER_3(vrlh, void, avr, avr, avr)
DEF_HELPER_3(vrlw, void, avr, avr, avr)
+DEF_HELPER_3(vsl, void, avr, avr, avr)
+DEF_HELPER_3(vsr, void, avr, avr, avr)
DEF_HELPER_4(vsldoi, void, avr, avr, avr, i32)
DEF_HELPER_3(vspltb, void, avr, avr, i32)
DEF_HELPER_3(vsplth, void, avr, avr, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index ef19bde..81abd63 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2491,6 +2491,45 @@ void helper_vsel (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
r->u64[1] = (a->u64[1] & ~c->u64[1]) | (b->u64[1] & c->u64[1]);
}
+#if defined(WORDS_BIGENDIAN)
+#define LEFT 0
+#define RIGHT 1
+#else
+#define LEFT 1
+#define RIGHT 0
+#endif
+/* The specification says that the results are undefined if all of the
+ * shift counts are not identical. We check to make sure that they are
+ * to conform to what real hardware appears to do. */
+#define VSHIFT(suffix, leftp) \
+ void helper_vs##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+ { \
+ int shift = b->u8[LO_IDX*0x15] & 0x7; \
+ int doit = 1; \
+ int i; \
+ for (i = 0; i < ARRAY_SIZE(r->u8); i++) { \
+ doit = doit && ((b->u8[i] & 0x7) == shift); \
+ } \
+ if (doit) { \
+ if (shift == 0) { \
+ *r = *a; \
+ } else if (leftp) { \
+ uint64_t carry = a->u64[LO_IDX] >> (64 - shift); \
+ r->u64[HI_IDX] = (a->u64[HI_IDX] << shift) | carry; \
+ r->u64[LO_IDX] = a->u64[LO_IDX] << shift; \
+ } else { \
+ uint64_t carry = a->u64[HI_IDX] << (64 - shift); \
+ r->u64[LO_IDX] = (a->u64[LO_IDX] >> shift) | carry; \
+ r->u64[HI_IDX] = a->u64[HI_IDX] >> shift; \
+ } \
+ } \
+ }
+VSHIFT(l, LEFT)
+VSHIFT(r, RIGHT)
+#undef VSHIFT
+#undef LEFT
+#undef RIGHT
+
#define VSL(suffix, element) \
void helper_vsl##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index e92156f..65a80f2 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6356,6 +6356,8 @@ GEN_VXFORM(vsubsws, 0, 30);
GEN_VXFORM(vrlb, 2, 0);
GEN_VXFORM(vrlh, 2, 1);
GEN_VXFORM(vrlw, 2, 2);
+GEN_VXFORM(vsl, 2, 7);
+GEN_VXFORM(vsr, 2, 11);
GEN_VXFORM(vpkuhum, 7, 0);
GEN_VXFORM(vpkuwum, 7, 1);
GEN_VXFORM(vpkuhus, 7, 2);
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH 20/40] Add vs{l,r} instructions.
2009-01-07 21:25 ` Nathan Froyd
@ 2009-01-08 18:56 ` Aurelien Jarno
0 siblings, 0 replies; 68+ messages in thread
From: Aurelien Jarno @ 2009-01-08 18:56 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Wed, Jan 07, 2009 at 01:25:02PM -0800, Nathan Froyd wrote:
> On Mon, Jan 05, 2009 at 08:27:30PM +0100, Aurelien Jarno wrote:
> > On Mon, Jan 05, 2009 at 10:29:56AM -0800, Nathan Froyd wrote:
> > > FWIW, doing the check has the nice property of delivering the same
> > > results as real hardware. If you're using a comparison program like
> > > ppctester, reducing those spurious failures is a win. (There's already
> > > spurious failures for div instructions in corner cases.)
> >
> > Then I am fine with that. Could you please just add a comment that it is
> > not necessary according to the spec, but done to match real hardware?
>
> Done thusly.
Thanks, applied
> -Nathan
>
> From aa19aa5e31aa9eec36a2cdfb2e1ed806555eda96 Mon Sep 17 00:00:00 2001
> From: Nathan Froyd <froydnj@codesourcery.com>
> Date: Thu, 11 Dec 2008 12:02:03 -0800
> Subject: [PATCH 4/5] Add vs{l,r} instructions.
>
> Add explanatory comment about why we check equality of shift counts.
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/helper.h | 2 ++
> target-ppc/op_helper.c | 39 +++++++++++++++++++++++++++++++++++++++
> target-ppc/translate.c | 2 ++
> 3 files changed, 43 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 009f516..e15d6b0 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -185,6 +185,8 @@ DEF_HELPER_3(vsubuws, void, avr, avr, avr)
> DEF_HELPER_3(vrlb, void, avr, avr, avr)
> DEF_HELPER_3(vrlh, void, avr, avr, avr)
> DEF_HELPER_3(vrlw, void, avr, avr, avr)
> +DEF_HELPER_3(vsl, void, avr, avr, avr)
> +DEF_HELPER_3(vsr, void, avr, avr, avr)
> DEF_HELPER_4(vsldoi, void, avr, avr, avr, i32)
> DEF_HELPER_3(vspltb, void, avr, avr, i32)
> DEF_HELPER_3(vsplth, void, avr, avr, i32)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index ef19bde..81abd63 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2491,6 +2491,45 @@ void helper_vsel (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> r->u64[1] = (a->u64[1] & ~c->u64[1]) | (b->u64[1] & c->u64[1]);
> }
>
> +#if defined(WORDS_BIGENDIAN)
> +#define LEFT 0
> +#define RIGHT 1
> +#else
> +#define LEFT 1
> +#define RIGHT 0
> +#endif
> +/* The specification says that the results are undefined if all of the
> + * shift counts are not identical. We check to make sure that they are
> + * to conform to what real hardware appears to do. */
> +#define VSHIFT(suffix, leftp) \
> + void helper_vs##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> + { \
> + int shift = b->u8[LO_IDX*0x15] & 0x7; \
> + int doit = 1; \
> + int i; \
> + for (i = 0; i < ARRAY_SIZE(r->u8); i++) { \
> + doit = doit && ((b->u8[i] & 0x7) == shift); \
> + } \
> + if (doit) { \
> + if (shift == 0) { \
> + *r = *a; \
> + } else if (leftp) { \
> + uint64_t carry = a->u64[LO_IDX] >> (64 - shift); \
> + r->u64[HI_IDX] = (a->u64[HI_IDX] << shift) | carry; \
> + r->u64[LO_IDX] = a->u64[LO_IDX] << shift; \
> + } else { \
> + uint64_t carry = a->u64[HI_IDX] << (64 - shift); \
> + r->u64[LO_IDX] = (a->u64[LO_IDX] >> shift) | carry; \
> + r->u64[HI_IDX] = a->u64[HI_IDX] >> shift; \
> + } \
> + } \
> + }
> +VSHIFT(l, LEFT)
> +VSHIFT(r, RIGHT)
> +#undef VSHIFT
> +#undef LEFT
> +#undef RIGHT
> +
> #define VSL(suffix, element) \
> void helper_vsl##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> { \
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index e92156f..65a80f2 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6356,6 +6356,8 @@ GEN_VXFORM(vsubsws, 0, 30);
> GEN_VXFORM(vrlb, 2, 0);
> GEN_VXFORM(vrlh, 2, 1);
> GEN_VXFORM(vrlw, 2, 2);
> +GEN_VXFORM(vsl, 2, 7);
> +GEN_VXFORM(vsr, 2, 11);
> GEN_VXFORM(vpkuhum, 7, 0);
> GEN_VXFORM(vpkuwum, 7, 1);
> GEN_VXFORM(vpkuhus, 7, 2);
> --
> 1.6.0.5
>
>
>
>
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 21/40] Add vsldoi instruction.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (19 preceding siblings ...)
2008-12-31 3:10 ` [Qemu-devel] [PATCH 20/40] Add vs{l,r} instructions Nathan Froyd
@ 2008-12-31 3:10 ` Nathan Froyd
2008-12-31 3:10 ` [Qemu-devel] [PATCH 22/40] Add GEN_VXFORM_SIMM macro for subsequent instructions Nathan Froyd
` (19 subsequent siblings)
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:10 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 1 +
target-ppc/op_helper.c | 28 ++++++++++++++++++++++++++++
target-ppc/translate.c | 21 +++++++++++++++++++++
3 files changed, 50 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 5f94e9f..02e3c10 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -178,6 +178,7 @@ DEF_HELPER_3(vrlh, void, avr, avr, avr)
DEF_HELPER_3(vrlw, void, avr, avr, avr)
DEF_HELPER_3(vsl, void, avr, avr, avr)
DEF_HELPER_3(vsr, void, avr, avr, avr)
+DEF_HELPER_4(vsldoi, void, avr, avr, avr, i32)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index ce47ef1..d0748b2 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2261,6 +2261,34 @@ VSL(h, u16)
VSL(w, u32)
#undef VSL
+void helper_vsldoi (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t shift)
+{
+ int sh = shift & 0xf;
+ int i;
+ ppc_avr_t result;
+
+#if defined(WORDS_BIGENDIAN)
+ for (i = 0; i < ARRAY_SIZE(r->u8); i++) {
+ int index = sh + i;
+ if (index > 0xf) {
+ result.u8[i] = b->u8[index-0x10];
+ } else {
+ result.u8[i] = a->u8[index];
+ }
+ }
+#else
+ for (i = 0; i < ARRAY_SIZE(r->u8); i++) {
+ int index = (16 - sh) + i;
+ if (index > 0xf) {
+ result.u8[i] = a->u8[index-0x10];
+ } else {
+ result.u8[i] = b->u8[index];
+ }
+ }
+#endif
+ *r = result;
+}
+
void helper_vslo (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
{
int sh = (b->u8[LO_IDX*0xf] >> 3) & 0xf;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index b50aba3..4516ba6 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -374,6 +374,8 @@ EXTRACT_HELPER(UIMM, 0, 16);
EXTRACT_HELPER(NB, 11, 5);
/* Shift count */
EXTRACT_HELPER(SH, 11, 5);
+/* Vector shift count */
+EXTRACT_HELPER(VSH, 6, 4);
/* Mask start */
EXTRACT_HELPER(MB, 6, 5);
/* Mask end */
@@ -6356,6 +6358,25 @@ GEN_VXRFORM(vcmpgtub, 3, 8)
GEN_VXRFORM(vcmpgtuh, 3, 9)
GEN_VXRFORM(vcmpgtuw, 3, 10)
+GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
+{
+ TCGv_ptr ra, rb, rd;
+ TCGv sh;
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+ ra = gen_avr_ptr(rA(ctx->opcode));
+ rb = gen_avr_ptr(rB(ctx->opcode));
+ rd = gen_avr_ptr(rD(ctx->opcode));
+ sh = tcg_const_i32(VSH(ctx->opcode));
+ gen_helper_vsldoi (rd, ra, rb, sh);
+ tcg_temp_free_ptr(ra);
+ tcg_temp_free_ptr(rb);
+ tcg_temp_free_ptr(rd);
+ tcg_temp_free(sh);
+}
+
/*** SPE extension ***/
/* Register moves */
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [PATCH 22/40] Add GEN_VXFORM_SIMM macro for subsequent instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (20 preceding siblings ...)
2008-12-31 3:10 ` [Qemu-devel] [PATCH 21/40] Add vsldoi instruction Nathan Froyd
@ 2008-12-31 3:10 ` Nathan Froyd
2008-12-31 3:10 ` [Qemu-devel] [PATCH 23/40] Add vspltis{b,h,w} instructions Nathan Froyd
` (18 subsequent siblings)
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:10 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/translate.c | 18 ++++++++++++++++++
1 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 4516ba6..e590476 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -370,6 +370,8 @@ EXTRACT_HELPER(IMM, 12, 8);
EXTRACT_SHELPER(SIMM, 0, 16);
/* 16 bits unsigned immediate value */
EXTRACT_HELPER(UIMM, 0, 16);
+/* 5 bits signed immediate value */
+EXTRACT_HELPER(SIMM5, 16, 5);
/* Bit count */
EXTRACT_HELPER(NB, 11, 5);
/* Shift count */
@@ -6321,6 +6323,22 @@ GEN_VXFORM(vrlw, 2, 2);
GEN_VXFORM(vsl, 2, 7);
GEN_VXFORM(vsr, 2, 11);
+#define GEN_VXFORM_SIMM(name, opc2, opc3) \
+ GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
+ { \
+ TCGv_ptr rd; \
+ TCGv_i32 simm; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ simm = tcg_const_i32(SIMM5(ctx->opcode)); \
+ rd = gen_avr_ptr(rD(ctx->opcode)); \
+ gen_helper_##name (rd, simm); \
+ tcg_temp_free_i32(simm); \
+ tcg_temp_free_ptr(rd); \
+ }
+
#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
{ \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [PATCH 23/40] Add vspltis{b,h,w} instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (21 preceding siblings ...)
2008-12-31 3:10 ` [Qemu-devel] [PATCH 22/40] Add GEN_VXFORM_SIMM macro for subsequent instructions Nathan Froyd
@ 2008-12-31 3:10 ` Nathan Froyd
2009-01-03 21:43 ` Aurelien Jarno
2008-12-31 3:10 ` [Qemu-devel] [PATCH 24/40] Add GEN_VXFORM_UIMM macro for subsequent instructions Nathan Froyd
` (17 subsequent siblings)
40 siblings, 1 reply; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:10 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 3 +++
target-ppc/op_helper.c | 17 +++++++++++++++++
target-ppc/translate.c | 4 ++++
3 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 02e3c10..9fbcc4a 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -179,6 +179,9 @@ DEF_HELPER_3(vrlw, void, avr, avr, avr)
DEF_HELPER_3(vsl, void, avr, avr, avr)
DEF_HELPER_3(vsr, void, avr, avr, avr)
DEF_HELPER_4(vsldoi, void, avr, avr, avr, i32)
+DEF_HELPER_2(vspltisb, void, avr, i32)
+DEF_HELPER_2(vspltish, void, avr, i32)
+DEF_HELPER_2(vspltisw, void, avr, i32)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index d0748b2..55f341f 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2302,6 +2302,23 @@ void helper_vslo (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
#endif
}
+#define VSPLTI(suffix, element, splat_type) \
+ void helper_vspltis##suffix (ppc_avr_t *r, uint32_t splat) \
+ { \
+ splat_type x = (splat_type)splat; \
+ int i; \
+ /* 5-bit sign extension. */ \
+ if (x & 0x10) \
+ x -= 0x20; \
+ for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
+ r->element[i] = x; \
+ } \
+ }
+VSPLTI(b, s8, int8_t)
+VSPLTI(h, s16, int16_t)
+VSPLTI(w, s32, int32_t)
+#undef VSPLTI
+
#define VSR(suffix, element) \
void helper_vsr##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index e590476..d9c1e60 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6339,6 +6339,10 @@ GEN_VXFORM(vsr, 2, 11);
tcg_temp_free_ptr(rd); \
}
+GEN_VXFORM_SIMM(vspltisb, 6, 12);
+GEN_VXFORM_SIMM(vspltish, 6, 13);
+GEN_VXFORM_SIMM(vspltisw, 6, 14);
+
#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
{ \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH 23/40] Add vspltis{b,h,w} instructions.
2008-12-31 3:10 ` [Qemu-devel] [PATCH 23/40] Add vspltis{b,h,w} instructions Nathan Froyd
@ 2009-01-03 21:43 ` Aurelien Jarno
2009-01-07 21:25 ` Nathan Froyd
0 siblings, 1 reply; 68+ messages in thread
From: Aurelien Jarno @ 2009-01-03 21:43 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Tue, Dec 30, 2008 at 07:10:05PM -0800, Nathan Froyd wrote:
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/helper.h | 3 +++
> target-ppc/op_helper.c | 17 +++++++++++++++++
> target-ppc/translate.c | 4 ++++
> 3 files changed, 24 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 02e3c10..9fbcc4a 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -179,6 +179,9 @@ DEF_HELPER_3(vrlw, void, avr, avr, avr)
> DEF_HELPER_3(vsl, void, avr, avr, avr)
> DEF_HELPER_3(vsr, void, avr, avr, avr)
> DEF_HELPER_4(vsldoi, void, avr, avr, avr, i32)
> +DEF_HELPER_2(vspltisb, void, avr, i32)
> +DEF_HELPER_2(vspltish, void, avr, i32)
> +DEF_HELPER_2(vspltisw, void, avr, i32)
>
> DEF_HELPER_1(efscfsi, i32, i32)
> DEF_HELPER_1(efscfui, i32, i32)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index d0748b2..55f341f 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2302,6 +2302,23 @@ void helper_vslo (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
> #endif
> }
>
> +#define VSPLTI(suffix, element, splat_type) \
> + void helper_vspltis##suffix (ppc_avr_t *r, uint32_t splat) \
> + { \
> + splat_type x = (splat_type)splat; \
> + int i; \
> + /* 5-bit sign extension. */ \
> + if (x & 0x10) \
> + x -= 0x20; \
I don't really like this way of doing a sign extension. I would prefer
to avoid a test and do something like:
splat_type x = (int8_t)(splat << 3) >> 3;
> + for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
> + r->element[i] = x; \
> + } \
> + }
> +VSPLTI(b, s8, int8_t)
> +VSPLTI(h, s16, int16_t)
> +VSPLTI(w, s32, int32_t)
> +#undef VSPLTI
> +
> #define VSR(suffix, element) \
> void helper_vsr##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> { \
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index e590476..d9c1e60 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6339,6 +6339,10 @@ GEN_VXFORM(vsr, 2, 11);
> tcg_temp_free_ptr(rd); \
> }
>
> +GEN_VXFORM_SIMM(vspltisb, 6, 12);
> +GEN_VXFORM_SIMM(vspltish, 6, 13);
> +GEN_VXFORM_SIMM(vspltisw, 6, 14);
> +
> #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
> GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
> { \
> --
> 1.6.0.5
>
>
>
>
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH 23/40] Add vspltis{b,h,w} instructions.
2009-01-03 21:43 ` Aurelien Jarno
@ 2009-01-07 21:25 ` Nathan Froyd
2009-01-08 18:57 ` Aurelien Jarno
0 siblings, 1 reply; 68+ messages in thread
From: Nathan Froyd @ 2009-01-07 21:25 UTC (permalink / raw)
To: qemu-devel
On Sat, Jan 03, 2009 at 10:43:54PM +0100, Aurelien Jarno wrote:
> On Tue, Dec 30, 2008 at 07:10:05PM -0800, Nathan Froyd wrote:
> > +#define VSPLTI(suffix, element, splat_type) \
> > + void helper_vspltis##suffix (ppc_avr_t *r, uint32_t splat) \
> > + { \
> > + splat_type x = (splat_type)splat; \
> > + int i; \
> > + /* 5-bit sign extension. */ \
> > + if (x & 0x10) \
> > + x -= 0x20; \
>
> I don't really like this way of doing a sign extension. I would prefer
> to avoid a test and do something like:
> splat_type x = (int8_t)(splat << 3) >> 3;
Done thusly.
-Nathan
Use more obvious sequence for 5-bit sign extension.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 3 +++
target-ppc/op_helper.c | 14 ++++++++++++++
target-ppc/translate.c | 20 ++++++++++++++++++++
3 files changed, 37 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index e15d6b0..755bfba 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -188,6 +188,9 @@ DEF_HELPER_3(vrlw, void, avr, avr, avr)
DEF_HELPER_3(vsl, void, avr, avr, avr)
DEF_HELPER_3(vsr, void, avr, avr, avr)
DEF_HELPER_4(vsldoi, void, avr, avr, avr, i32)
+DEF_HELPER_2(vspltisb, void, avr, i32)
+DEF_HELPER_2(vspltish, void, avr, i32)
+DEF_HELPER_2(vspltisw, void, avr, i32)
DEF_HELPER_3(vspltb, void, avr, avr, i32)
DEF_HELPER_3(vsplth, void, avr, avr, i32)
DEF_HELPER_3(vspltw, void, avr, avr, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 81abd63..dc8ddfe 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2609,6 +2609,20 @@ VSPLT(w, u32)
#undef SPLAT_ELEMENT
#undef _SPLAT_MASKED
+#define VSPLTI(suffix, element, splat_type) \
+ void helper_vspltis##suffix (ppc_avr_t *r, uint32_t splat) \
+ { \
+ splat_type x = (int8_t)(splat << 3) >> 3; \
+ int i; \
+ for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
+ r->element[i] = x; \
+ } \
+ }
+VSPLTI(b, s8, int8_t)
+VSPLTI(h, s16, int16_t)
+VSPLTI(w, s32, int32_t)
+#undef VSPLTI
+
#define VSR(suffix, element) \
void helper_vsr##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 65a80f2..6bb81d2 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6404,6 +6404,26 @@ GEN_VXRFORM(vcmpgtub, 3, 8)
GEN_VXRFORM(vcmpgtuh, 3, 9)
GEN_VXRFORM(vcmpgtuw, 3, 10)
+#define GEN_VXFORM_SIMM(name, opc2, opc3) \
+ GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
+ { \
+ TCGv_ptr rd; \
+ TCGv_i32 simm; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ simm = tcg_const_i32(SIMM5(ctx->opcode)); \
+ rd = gen_avr_ptr(rD(ctx->opcode)); \
+ gen_helper_##name (rd, simm); \
+ tcg_temp_free_i32(simm); \
+ tcg_temp_free_ptr(rd); \
+ }
+
+GEN_VXFORM_SIMM(vspltisb, 6, 12);
+GEN_VXFORM_SIMM(vspltish, 6, 13);
+GEN_VXFORM_SIMM(vspltisw, 6, 14);
+
#define GEN_VXFORM_NOA(name, opc2, opc3) \
GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) \
{ \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH 23/40] Add vspltis{b,h,w} instructions.
2009-01-07 21:25 ` Nathan Froyd
@ 2009-01-08 18:57 ` Aurelien Jarno
0 siblings, 0 replies; 68+ messages in thread
From: Aurelien Jarno @ 2009-01-08 18:57 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Wed, Jan 07, 2009 at 01:25:32PM -0800, Nathan Froyd wrote:
> On Sat, Jan 03, 2009 at 10:43:54PM +0100, Aurelien Jarno wrote:
> > On Tue, Dec 30, 2008 at 07:10:05PM -0800, Nathan Froyd wrote:
> > > +#define VSPLTI(suffix, element, splat_type) \
> > > + void helper_vspltis##suffix (ppc_avr_t *r, uint32_t splat) \
> > > + { \
> > > + splat_type x = (splat_type)splat; \
> > > + int i; \
> > > + /* 5-bit sign extension. */ \
> > > + if (x & 0x10) \
> > > + x -= 0x20; \
> >
> > I don't really like this way of doing a sign extension. I would prefer
> > to avoid a test and do something like:
> > splat_type x = (int8_t)(splat << 3) >> 3;
>
> Done thusly.
Thanks, applied.
> -Nathan
>
> Use more obvious sequence for 5-bit sign extension.
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/helper.h | 3 +++
> target-ppc/op_helper.c | 14 ++++++++++++++
> target-ppc/translate.c | 20 ++++++++++++++++++++
> 3 files changed, 37 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index e15d6b0..755bfba 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -188,6 +188,9 @@ DEF_HELPER_3(vrlw, void, avr, avr, avr)
> DEF_HELPER_3(vsl, void, avr, avr, avr)
> DEF_HELPER_3(vsr, void, avr, avr, avr)
> DEF_HELPER_4(vsldoi, void, avr, avr, avr, i32)
> +DEF_HELPER_2(vspltisb, void, avr, i32)
> +DEF_HELPER_2(vspltish, void, avr, i32)
> +DEF_HELPER_2(vspltisw, void, avr, i32)
> DEF_HELPER_3(vspltb, void, avr, avr, i32)
> DEF_HELPER_3(vsplth, void, avr, avr, i32)
> DEF_HELPER_3(vspltw, void, avr, avr, i32)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index 81abd63..dc8ddfe 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2609,6 +2609,20 @@ VSPLT(w, u32)
> #undef SPLAT_ELEMENT
> #undef _SPLAT_MASKED
>
> +#define VSPLTI(suffix, element, splat_type) \
> + void helper_vspltis##suffix (ppc_avr_t *r, uint32_t splat) \
> + { \
> + splat_type x = (int8_t)(splat << 3) >> 3; \
> + int i; \
> + for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
> + r->element[i] = x; \
> + } \
> + }
> +VSPLTI(b, s8, int8_t)
> +VSPLTI(h, s16, int16_t)
> +VSPLTI(w, s32, int32_t)
> +#undef VSPLTI
> +
> #define VSR(suffix, element) \
> void helper_vsr##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> { \
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 65a80f2..6bb81d2 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6404,6 +6404,26 @@ GEN_VXRFORM(vcmpgtub, 3, 8)
> GEN_VXRFORM(vcmpgtuh, 3, 9)
> GEN_VXRFORM(vcmpgtuw, 3, 10)
>
> +#define GEN_VXFORM_SIMM(name, opc2, opc3) \
> + GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
> + { \
> + TCGv_ptr rd; \
> + TCGv_i32 simm; \
> + if (unlikely(!ctx->altivec_enabled)) { \
> + gen_exception(ctx, POWERPC_EXCP_VPU); \
> + return; \
> + } \
> + simm = tcg_const_i32(SIMM5(ctx->opcode)); \
> + rd = gen_avr_ptr(rD(ctx->opcode)); \
> + gen_helper_##name (rd, simm); \
> + tcg_temp_free_i32(simm); \
> + tcg_temp_free_ptr(rd); \
> + }
> +
> +GEN_VXFORM_SIMM(vspltisb, 6, 12);
> +GEN_VXFORM_SIMM(vspltish, 6, 13);
> +GEN_VXFORM_SIMM(vspltisw, 6, 14);
> +
> #define GEN_VXFORM_NOA(name, opc2, opc3) \
> GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) \
> { \
> --
> 1.6.0.5
>
>
>
>
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [PATCH 24/40] Add GEN_VXFORM_UIMM macro for subsequent instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (22 preceding siblings ...)
2008-12-31 3:10 ` [Qemu-devel] [PATCH 23/40] Add vspltis{b,h,w} instructions Nathan Froyd
@ 2008-12-31 3:10 ` Nathan Froyd
2008-12-31 3:10 ` [Qemu-devel] [PATCH 25/40] Add vsplt{b,h,w} instructions Nathan Froyd
` (16 subsequent siblings)
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:10 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/translate.c | 20 ++++++++++++++++++++
1 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index d9c1e60..77e93cb 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -372,6 +372,8 @@ EXTRACT_SHELPER(SIMM, 0, 16);
EXTRACT_HELPER(UIMM, 0, 16);
/* 5 bits signed immediate value */
EXTRACT_HELPER(SIMM5, 16, 5);
+/* 5 bits signed immediate value */
+EXTRACT_HELPER(UIMM5, 16, 5);
/* Bit count */
EXTRACT_HELPER(NB, 11, 5);
/* Shift count */
@@ -6343,6 +6345,24 @@ GEN_VXFORM_SIMM(vspltisb, 6, 12);
GEN_VXFORM_SIMM(vspltish, 6, 13);
GEN_VXFORM_SIMM(vspltisw, 6, 14);
+#define GEN_VXFORM_UIMM(name, opc2, opc3) \
+ GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
+ { \
+ TCGv_ptr rb, rd; \
+ TCGv_i32 uimm; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
+ rb = gen_avr_ptr(rB(ctx->opcode)); \
+ rd = gen_avr_ptr(rD(ctx->opcode)); \
+ gen_helper_##name (rd, rb, uimm); \
+ tcg_temp_free_i32(uimm); \
+ tcg_temp_free_ptr(rb); \
+ tcg_temp_free_ptr(rd); \
+ }
+
#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
{ \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [PATCH 25/40] Add vsplt{b,h,w} instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (23 preceding siblings ...)
2008-12-31 3:10 ` [Qemu-devel] [PATCH 24/40] Add GEN_VXFORM_UIMM macro for subsequent instructions Nathan Froyd
@ 2008-12-31 3:10 ` Nathan Froyd
2008-12-31 3:10 ` [Qemu-devel] [PATCH 26/40] Add GEN_VXFORM_NOA macro for subsequent instructions Nathan Froyd
` (15 subsequent siblings)
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:10 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 3 +++
target-ppc/op_helper.c | 23 +++++++++++++++++++++++
target-ppc/translate.c | 4 ++++
3 files changed, 30 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 9fbcc4a..2ca4e26 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -182,6 +182,9 @@ DEF_HELPER_4(vsldoi, void, avr, avr, avr, i32)
DEF_HELPER_2(vspltisb, void, avr, i32)
DEF_HELPER_2(vspltish, void, avr, i32)
DEF_HELPER_2(vspltisw, void, avr, i32)
+DEF_HELPER_3(vspltb, void, avr, avr, i32)
+DEF_HELPER_3(vsplth, void, avr, avr, i32)
+DEF_HELPER_3(vspltw, void, avr, avr, i32)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 55f341f..28b1fb6 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2302,6 +2302,29 @@ void helper_vslo (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
#endif
}
+/* Experimental testing shows that hardware masks the immediate. */
+#define _SPLAT_MASKED(element) (splat & (ARRAY_SIZE(r->element) - 1))
+#if defined(WORDS_BIGENDIAN)
+#define SPLAT_ELEMENT(element) _SPLAT_MASKED(element)
+#else
+#define SPLAT_ELEMENT(element) (ARRAY_SIZE(r->element)-1 - _SPLAT_MASKED(element))
+#endif
+#define VSPLT(suffix, element) \
+ void helper_vsplt##suffix (ppc_avr_t *r, ppc_avr_t *b, uint32_t splat) \
+ { \
+ uint32_t s = b->element[SPLAT_ELEMENT(element)]; \
+ int i; \
+ for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
+ r->element[i] = s; \
+ } \
+ }
+VSPLT(b, u8)
+VSPLT(h, u16)
+VSPLT(w, u32)
+#undef VSPLT
+#undef SPLAT_ELEMENT
+#undef _SPLAT_MASKED
+
#define VSPLTI(suffix, element, splat_type) \
void helper_vspltis##suffix (ppc_avr_t *r, uint32_t splat) \
{ \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 77e93cb..bade2c8 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6363,6 +6363,10 @@ GEN_VXFORM_SIMM(vspltisw, 6, 14);
tcg_temp_free_ptr(rd); \
}
+GEN_VXFORM_UIMM(vspltb, 6, 8);
+GEN_VXFORM_UIMM(vsplth, 6, 9);
+GEN_VXFORM_UIMM(vspltw, 6, 10);
+
#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
{ \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [PATCH 26/40] Add GEN_VXFORM_NOA macro for subsequent instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (24 preceding siblings ...)
2008-12-31 3:10 ` [Qemu-devel] [PATCH 25/40] Add vsplt{b,h,w} instructions Nathan Froyd
@ 2008-12-31 3:10 ` Nathan Froyd
2008-12-31 3:10 ` [Qemu-devel] [PATCH 27/40] Add vupk{h,l}px instructions Nathan Froyd
` (14 subsequent siblings)
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:10 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/translate.c | 15 +++++++++++++++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index bade2c8..b8a7cab 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6325,6 +6325,21 @@ GEN_VXFORM(vrlw, 2, 2);
GEN_VXFORM(vsl, 2, 7);
GEN_VXFORM(vsr, 2, 11);
+#define GEN_VXFORM_NOA(name, opc2, opc3) \
+ GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) \
+ { \
+ TCGv_ptr rb, rd; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ rb = gen_avr_ptr(rB(ctx->opcode)); \
+ rd = gen_avr_ptr(rD(ctx->opcode)); \
+ gen_helper_##name (rd, rb); \
+ tcg_temp_free_ptr(rb); \
+ tcg_temp_free_ptr(rd); \
+ }
+
#define GEN_VXFORM_SIMM(name, opc2, opc3) \
GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
{ \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [PATCH 27/40] Add vupk{h,l}px instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (25 preceding siblings ...)
2008-12-31 3:10 ` [Qemu-devel] [PATCH 26/40] Add GEN_VXFORM_NOA macro for subsequent instructions Nathan Froyd
@ 2008-12-31 3:10 ` Nathan Froyd
2008-12-31 3:10 ` [Qemu-devel] [PATCH 28/40] Add vupk{h,l}s{b,h} instructions Nathan Froyd
` (13 subsequent siblings)
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:10 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 2 ++
target-ppc/op_helper.c | 29 +++++++++++++++++++++++++++++
target-ppc/translate.c | 3 +++
3 files changed, 34 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 2ca4e26..9352a67 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -185,6 +185,8 @@ DEF_HELPER_2(vspltisw, void, avr, i32)
DEF_HELPER_3(vspltb, void, avr, avr, i32)
DEF_HELPER_3(vsplth, void, avr, avr, i32)
DEF_HELPER_3(vspltw, void, avr, avr, i32)
+DEF_HELPER_2(vupkhpx, void, avr, avr)
+DEF_HELPER_2(vupklpx, void, avr, avr)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 28b1fb6..5d8e678 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2381,6 +2381,35 @@ void helper_vsubcuw (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
}
}
+#if defined(WORDS_BIGENDIAN)
+#define UPKHI 1
+#define UPKLO 0
+#else
+#define UPKHI 0
+#define UPKLO 1
+#endif
+#define VUPKPX(suffix, hi) \
+ void helper_vupk##suffix (ppc_avr_t *r, ppc_avr_t *b) \
+ { \
+ int i; \
+ ppc_avr_t result; \
+ for (i = 0; i < ARRAY_SIZE(r->u32); i++) { \
+ uint16_t e = b->u16[hi ? i : i+4]; \
+ uint8_t a = (e >> 15) ? 0xff : 0; \
+ uint8_t r = (e >> 10) & 0x1f; \
+ uint8_t g = (e >> 5) & 0x1f; \
+ uint8_t b = e & 0x1f; \
+ result.u32[i] = (a << 24) | (r << 16) | (g << 8) | b; \
+ } \
+ *r = result; \
+ }
+VUPKPX(lpx, UPKLO)
+VUPKPX(hpx, UPKHI)
+#undef VUPKPX
+
+#undef UPKHI
+#undef UPKLO
+
#undef VECTOR_FOR_INORDER_I
#undef HI_IDX
#undef LO_IDX
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index b8a7cab..a280db1 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6340,6 +6340,9 @@ GEN_VXFORM(vsr, 2, 11);
tcg_temp_free_ptr(rd); \
}
+GEN_VXFORM_NOA(vupkhpx, 7, 13);
+GEN_VXFORM_NOA(vupklpx, 7, 15);
+
#define GEN_VXFORM_SIMM(name, opc2, opc3) \
GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
{ \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [PATCH 28/40] Add vupk{h,l}s{b,h} instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (26 preceding siblings ...)
2008-12-31 3:10 ` [Qemu-devel] [PATCH 27/40] Add vupk{h,l}px instructions Nathan Froyd
@ 2008-12-31 3:10 ` Nathan Froyd
2008-12-31 3:10 ` [Qemu-devel] [PATCH 29/40] Add GEN_VAFORM_PAIRED macro for subsequent instructions Nathan Froyd
` (12 subsequent siblings)
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:10 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 4 ++++
target-ppc/op_helper.c | 21 +++++++++++++++++++++
target-ppc/translate.c | 4 ++++
3 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 9352a67..26ff038 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -187,6 +187,10 @@ DEF_HELPER_3(vsplth, void, avr, avr, i32)
DEF_HELPER_3(vspltw, void, avr, avr, i32)
DEF_HELPER_2(vupkhpx, void, avr, avr)
DEF_HELPER_2(vupklpx, void, avr, avr)
+DEF_HELPER_2(vupkhsb, void, avr, avr)
+DEF_HELPER_2(vupkhsh, void, avr, avr)
+DEF_HELPER_2(vupklsb, void, avr, avr)
+DEF_HELPER_2(vupklsh, void, avr, avr)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 5d8e678..29c1f5d 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2407,6 +2407,27 @@ VUPKPX(lpx, UPKLO)
VUPKPX(hpx, UPKHI)
#undef VUPKPX
+#define VUPK(suffix, unpacked, packee, hi) \
+ void helper_vupk##suffix (ppc_avr_t *r, ppc_avr_t *b) \
+ { \
+ int i; \
+ ppc_avr_t result; \
+ if (hi) { \
+ for (i = 0; i < ARRAY_SIZE(r->unpacked); i++) { \
+ result.unpacked[i] = b->packee[i]; \
+ } \
+ } else { \
+ for (i = ARRAY_SIZE(r->unpacked); i < ARRAY_SIZE(r->packee); i++) { \
+ result.unpacked[i-ARRAY_SIZE(r->unpacked)] = b->packee[i]; \
+ } \
+ } \
+ *r = result; \
+ }
+VUPK(hsb, s16, s8, UPKHI)
+VUPK(hsh, s32, s16, UPKHI)
+VUPK(lsb, s16, s8, UPKLO)
+VUPK(lsh, s32, s16, UPKLO)
+#undef VUPK
#undef UPKHI
#undef UPKLO
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index a280db1..17784d7 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6340,6 +6340,10 @@ GEN_VXFORM(vsr, 2, 11);
tcg_temp_free_ptr(rd); \
}
+GEN_VXFORM_NOA(vupkhsb, 7, 8);
+GEN_VXFORM_NOA(vupkhsh, 7, 9);
+GEN_VXFORM_NOA(vupklsb, 7, 10);
+GEN_VXFORM_NOA(vupklsh, 7, 11);
GEN_VXFORM_NOA(vupkhpx, 7, 13);
GEN_VXFORM_NOA(vupklpx, 7, 15);
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [PATCH 29/40] Add GEN_VAFORM_PAIRED macro for subsequent instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (27 preceding siblings ...)
2008-12-31 3:10 ` [Qemu-devel] [PATCH 28/40] Add vupk{h,l}s{b,h} instructions Nathan Froyd
@ 2008-12-31 3:10 ` Nathan Froyd
2008-12-31 3:10 ` [Qemu-devel] [PATCH 30/40] Add vmsum{u,m}bm instructions Nathan Froyd
` (11 subsequent siblings)
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:10 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/translate.c | 23 +++++++++++++++++++++++
1 files changed, 23 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 17784d7..94086b3 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6445,6 +6445,29 @@ GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
tcg_temp_free(sh);
}
+#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
+ GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) \
+ { \
+ TCGv_ptr ra, rb, rc, rd; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ ra = gen_avr_ptr(rA(ctx->opcode)); \
+ rb = gen_avr_ptr(rB(ctx->opcode)); \
+ rc = gen_avr_ptr(rC(ctx->opcode)); \
+ rd = gen_avr_ptr(rD(ctx->opcode)); \
+ if (Rc(ctx->opcode)) { \
+ gen_helper_##name1 (rd, ra, rb, rc); \
+ } else { \
+ gen_helper_##name0 (rd, ra, rb, rc); \
+ } \
+ tcg_temp_free_ptr(ra); \
+ tcg_temp_free_ptr(rb); \
+ tcg_temp_free_ptr(rc); \
+ tcg_temp_free_ptr(rd); \
+ }
+
/*** SPE extension ***/
/* Register moves */
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [PATCH 30/40] Add vmsum{u,m}bm instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (28 preceding siblings ...)
2008-12-31 3:10 ` [Qemu-devel] [PATCH 29/40] Add GEN_VAFORM_PAIRED macro for subsequent instructions Nathan Froyd
@ 2008-12-31 3:10 ` Nathan Froyd
2008-12-31 3:10 ` [Qemu-devel] [PATCH 31/40] Add vsel and vperm instructions Nathan Froyd
` (10 subsequent siblings)
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:10 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 2 ++
target-ppc/op_helper.c | 28 ++++++++++++++++++++++++++++
target-ppc/translate.c | 2 ++
3 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 26ff038..dbd00f5 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -191,6 +191,8 @@ DEF_HELPER_2(vupkhsb, void, avr, avr)
DEF_HELPER_2(vupkhsh, void, avr, avr)
DEF_HELPER_2(vupklsb, void, avr, avr)
DEF_HELPER_2(vupklsh, void, avr, avr)
+DEF_HELPER_4(vmsumubm, void, avr, avr, avr, avr)
+DEF_HELPER_4(vmsummbm, void, avr, avr, avr, avr)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 29c1f5d..7b4824e 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2173,6 +2173,34 @@ VMRG(w, u32)
#undef MRGHI
#undef MRGLO
+void helper_vmsummbm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
+{
+ int32_t prod[16];
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(r->s8); i++) {
+ prod[i] = (int32_t)a->s8[i] * b->u8[i];
+ }
+
+ VECTOR_FOR_INORDER_I(i, s32) {
+ r->s32[i] = c->s32[i] + prod[4*i] + prod[4*i+1] + prod[4*i+2] + prod[4*i+3];
+ }
+}
+
+void helper_vmsumubm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
+{
+ uint16_t prod[16];
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(r->u8); i++) {
+ prod[i] = a->u8[i] * b->u8[i];
+ }
+
+ VECTOR_FOR_INORDER_I(i, u32) {
+ r->u32[i] = c->u32[i] + prod[4*i] + prod[4*i+1] + prod[4*i+2] + prod[4*i+3];
+ }
+}
+
#define VMUL_DO(name, mul_element, prod_element, evenp) \
void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 94086b3..a73c4ad 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6468,6 +6468,8 @@ GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
tcg_temp_free_ptr(rd); \
}
+GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
+
/*** SPE extension ***/
/* Register moves */
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [PATCH 31/40] Add vsel and vperm instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (29 preceding siblings ...)
2008-12-31 3:10 ` [Qemu-devel] [PATCH 30/40] Add vmsum{u,m}bm instructions Nathan Froyd
@ 2008-12-31 3:10 ` Nathan Froyd
2008-12-31 3:10 ` [Qemu-devel] [PATCH 32/40] Add saturating arithmetic conversion functions for subsequent instructions Nathan Froyd
` (9 subsequent siblings)
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:10 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 2 ++
target-ppc/op_helper.c | 26 ++++++++++++++++++++++++++
target-ppc/translate.c | 1 +
3 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index dbd00f5..8bd8cf3 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -193,6 +193,8 @@ DEF_HELPER_2(vupklsb, void, avr, avr)
DEF_HELPER_2(vupklsh, void, avr, avr)
DEF_HELPER_4(vmsumubm, void, avr, avr, avr, avr)
DEF_HELPER_4(vmsummbm, void, avr, avr, avr, avr)
+DEF_HELPER_4(vsel, void, avr, avr, avr, avr)
+DEF_HELPER_4(vperm, void, avr, avr, avr, avr)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 7b4824e..7170d05 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2223,6 +2223,26 @@ VMUL(uh, u16, u32)
#undef VMUL_DO
#undef VMUL
+void helper_vperm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
+{
+ ppc_avr_t result;
+ int i;
+ VECTOR_FOR_INORDER_I (i, u8) {
+ int s = c->u8[i] & 0x1f;
+#if defined(WORDS_BIGENDIAN)
+ int index = s & 0xf;
+#else
+ int index = 15 - (s & 0xf);
+#endif
+ if (s & 0x10) {
+ result.u8[i] = b->u8[index];
+ } else {
+ result.u8[i] = a->u8[index];
+ }
+ }
+ *r = result;
+}
+
#define VROTATE(suffix, element) \
void helper_vrl##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
@@ -2238,6 +2258,12 @@ VROTATE(h, u16)
VROTATE(w, u32)
#undef VROTATE
+void helper_vsel (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
+{
+ r->u64[0] = (a->u64[0] & ~c->u64[0]) | (b->u64[0] & c->u64[0]);
+ r->u64[1] = (a->u64[1] & ~c->u64[1]) | (b->u64[1] & c->u64[1]);
+}
+
#if defined(WORDS_BIGENDIAN)
#define LEFT 0
#define RIGHT 1
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index a73c4ad..7cf2171 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6469,6 +6469,7 @@ GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
}
GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
+GEN_VAFORM_PAIRED(vsel, vperm, 21)
/*** SPE extension ***/
/* Register moves */
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [PATCH 32/40] Add saturating arithmetic conversion functions for subsequent instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (30 preceding siblings ...)
2008-12-31 3:10 ` [Qemu-devel] [PATCH 31/40] Add vsel and vperm instructions Nathan Froyd
@ 2008-12-31 3:10 ` Nathan Froyd
2008-12-31 3:10 ` [Qemu-devel] [PATCH 33/40] Add vpks{h, w}{s, u}s, vpku{h, w}us, and vpku{h, w}um instructions Nathan Froyd
` (8 subsequent siblings)
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:10 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/op_helper.c | 27 +++++++++++++++++++++++++++
1 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 7170d05..09e1368 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -1972,6 +1972,33 @@ target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_
for (index = ARRAY_SIZE(r->element)-1; index >= 0; index--)
#endif
+/* Saturating arithmetic helpers. */
+#define SATCVT(from, to, from_type, to_type, min, max, use_min, use_max) \
+ static always_inline to_type cvt##from##to (from_type x, int *sat) \
+ { \
+ to_type r; \
+ if (use_min && x < min) { \
+ r = min; \
+ *sat = 1; \
+ } else if (use_max && x > max) { \
+ r = max; \
+ *sat = 1; \
+ } else { \
+ r = x; \
+ } \
+ return r; \
+ }
+SATCVT(sh, sb, int16_t, int8_t, INT8_MIN, INT8_MAX, 1, 1)
+SATCVT(sw, sh, int32_t, int16_t, INT16_MIN, INT16_MAX, 1, 1)
+SATCVT(sd, sw, int64_t, int32_t, INT32_MIN, INT32_MAX, 1, 1)
+SATCVT(uh, ub, uint16_t, uint8_t, 0, UINT8_MAX, 0, 1)
+SATCVT(uw, uh, uint32_t, uint16_t, 0, UINT16_MAX, 0, 1)
+SATCVT(ud, uw, uint64_t, uint32_t, 0, UINT32_MAX, 0, 1)
+SATCVT(sh, ub, int16_t, uint8_t, 0, UINT8_MAX, 1, 1)
+SATCVT(sw, uh, int32_t, uint16_t, 0, UINT16_MAX, 1, 1)
+SATCVT(sd, uw, int64_t, uint32_t, 0, UINT32_MAX, 1, 1)
+#undef SATCVT
+
void helper_lvsl (ppc_avr_t *r, target_ulong sh)
{
int i, j = (sh & 0xf);
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [PATCH 33/40] Add vpks{h, w}{s, u}s, vpku{h, w}us, and vpku{h, w}um instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (31 preceding siblings ...)
2008-12-31 3:10 ` [Qemu-devel] [PATCH 32/40] Add saturating arithmetic conversion functions for subsequent instructions Nathan Froyd
@ 2008-12-31 3:10 ` Nathan Froyd
2008-12-31 3:10 ` [Qemu-devel] [PATCH 34/40] Add vpkpx instruction Nathan Froyd
` (7 subsequent siblings)
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:10 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 8 ++++++++
target-ppc/op_helper.c | 35 +++++++++++++++++++++++++++++++++++
target-ppc/translate.c | 8 ++++++++
3 files changed, 51 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 8bd8cf3..a1ef4df 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -195,6 +195,14 @@ DEF_HELPER_4(vmsumubm, void, avr, avr, avr, avr)
DEF_HELPER_4(vmsummbm, void, avr, avr, avr, avr)
DEF_HELPER_4(vsel, void, avr, avr, avr, avr)
DEF_HELPER_4(vperm, void, avr, avr, avr, avr)
+DEF_HELPER_3(vpkshss, void, avr, avr, avr)
+DEF_HELPER_3(vpkshus, void, avr, avr, avr)
+DEF_HELPER_3(vpkswss, void, avr, avr, avr)
+DEF_HELPER_3(vpkswus, void, avr, avr, avr)
+DEF_HELPER_3(vpkuhus, void, avr, avr, avr)
+DEF_HELPER_3(vpkuwus, void, avr, avr, avr)
+DEF_HELPER_3(vpkuhum, void, avr, avr, avr)
+DEF_HELPER_3(vpkuwum, void, avr, avr, avr)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 09e1368..c34e1ce 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2270,6 +2270,41 @@ void helper_vperm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
*r = result;
}
+#if defined(WORDS_BIGENDIAN)
+#define PKBIG 1
+#else
+#define PKBIG 0
+#endif
+#define VPK(suffix, from, to, cvt, dosat) \
+ void helper_vpk##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+ { \
+ int i; \
+ int sat = 0; \
+ ppc_avr_t result; \
+ ppc_avr_t *a0 = PKBIG ? a : b; \
+ ppc_avr_t *a1 = PKBIG ? b : a; \
+ VECTOR_FOR_INORDER_I (i, from) { \
+ result.to[i] = cvt(a0->from[i], &sat); \
+ result.to[i+ARRAY_SIZE(r->from)] = cvt(a1->from[i], &sat); \
+ } \
+ *r = result; \
+ if (dosat && sat) { \
+ env->vscr |= (1 << VSCR_SAT); \
+ } \
+ }
+#define I(x, y) (x)
+VPK(shss, s16, s8, cvtshsb, 1)
+VPK(shus, s16, u8, cvtshub, 1)
+VPK(swss, s32, s16, cvtswsh, 1)
+VPK(swus, s32, u16, cvtswuh, 1)
+VPK(uhus, u16, u8, cvtuhub, 1)
+VPK(uwus, u32, u16, cvtuwuh, 1)
+VPK(uhum, u16, u8, I, 0)
+VPK(uwum, u32, u16, I, 0)
+#undef I
+#undef VPK
+#undef PKBIG
+
#define VROTATE(suffix, element) \
void helper_vrl##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 7cf2171..cf69d91 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6324,6 +6324,14 @@ GEN_VXFORM(vrlh, 2, 1);
GEN_VXFORM(vrlw, 2, 2);
GEN_VXFORM(vsl, 2, 7);
GEN_VXFORM(vsr, 2, 11);
+GEN_VXFORM(vpkuhum, 7, 0);
+GEN_VXFORM(vpkuwum, 7, 1);
+GEN_VXFORM(vpkuhus, 7, 2);
+GEN_VXFORM(vpkuwus, 7, 3);
+GEN_VXFORM(vpkshus, 7, 4);
+GEN_VXFORM(vpkswus, 7, 5);
+GEN_VXFORM(vpkshss, 7, 6);
+GEN_VXFORM(vpkswss, 7, 7);
#define GEN_VXFORM_NOA(name, opc2, opc3) \
GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [PATCH 34/40] Add vpkpx instruction.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (32 preceding siblings ...)
2008-12-31 3:10 ` [Qemu-devel] [PATCH 33/40] Add vpks{h, w}{s, u}s, vpku{h, w}us, and vpku{h, w}um instructions Nathan Froyd
@ 2008-12-31 3:10 ` Nathan Froyd
2008-12-31 3:10 ` [Qemu-devel] [PATCH 35/40] Add vmh{,r}addshs instructions Nathan Froyd
` (6 subsequent siblings)
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:10 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 1 +
target-ppc/op_helper.c | 21 +++++++++++++++++++++
target-ppc/translate.c | 1 +
3 files changed, 23 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index a1ef4df..e2ad294 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -203,6 +203,7 @@ DEF_HELPER_3(vpkuhus, void, avr, avr, avr)
DEF_HELPER_3(vpkuwus, void, avr, avr, avr)
DEF_HELPER_3(vpkuhum, void, avr, avr, avr)
DEF_HELPER_3(vpkuwum, void, avr, avr, avr)
+DEF_HELPER_3(vpkpx, void, avr, avr, avr)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index c34e1ce..d64b05c 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2275,6 +2275,27 @@ void helper_vperm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
#else
#define PKBIG 0
#endif
+void helper_vpkpx (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ int i, j;
+ ppc_avr_t result;
+#if defined(WORDS_BIGENDIAN)
+ const ppc_avr_t *x[2] = { a, b };
+#else
+ const ppc_avr_t *x[2] = { b, a };
+#endif
+
+ VECTOR_FOR_INORDER_I (i, u64) {
+ VECTOR_FOR_INORDER_I (j, u32){
+ uint32_t e = x[i]->u32[j];
+ result.u16[4*i+j] = (((e >> 9) & 0xfc00) |
+ ((e >> 6) & 0x3e0) |
+ ((e >> 3) & 0x1f));
+ }
+ }
+ *r = result;
+}
+
#define VPK(suffix, from, to, cvt, dosat) \
void helper_vpk##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index cf69d91..bc1a1ff 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6332,6 +6332,7 @@ GEN_VXFORM(vpkshus, 7, 4);
GEN_VXFORM(vpkswus, 7, 5);
GEN_VXFORM(vpkshss, 7, 6);
GEN_VXFORM(vpkswss, 7, 7);
+GEN_VXFORM(vpkpx, 7, 12);
#define GEN_VXFORM_NOA(name, opc2, opc3) \
GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [PATCH 35/40] Add vmh{,r}addshs instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (33 preceding siblings ...)
2008-12-31 3:10 ` [Qemu-devel] [PATCH 34/40] Add vpkpx instruction Nathan Froyd
@ 2008-12-31 3:10 ` Nathan Froyd
2008-12-31 3:10 ` [Qemu-devel] [PATCH 36/40] Add vmsumuh{m,s} instructions Nathan Froyd
` (5 subsequent siblings)
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:10 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 2 ++
target-ppc/op_helper.c | 32 ++++++++++++++++++++++++++++++++
target-ppc/translate.c | 2 ++
3 files changed, 36 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index e2ad294..8ea8ddd 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -204,6 +204,8 @@ DEF_HELPER_3(vpkuwus, void, avr, avr, avr)
DEF_HELPER_3(vpkuhum, void, avr, avr, avr)
DEF_HELPER_3(vpkuwum, void, avr, avr, avr)
DEF_HELPER_3(vpkpx, void, avr, avr, avr)
+DEF_HELPER_4(vmhaddshs, void, avr, avr, avr, avr)
+DEF_HELPER_4(vmhraddshs, void, avr, avr, avr, avr)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index d64b05c..8c354c3 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2141,6 +2141,38 @@ VCMP(gtsh, >, s16)
VCMP(gtsw, >, s32)
#undef VCMP
+void helper_vmhaddshs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
+{
+ int sat = 0;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(r->s16); i++) {
+ int32_t prod = a->s16[i] * b->s16[i];
+ int32_t t = (int32_t)c->s16[i] + (prod >> 15);
+ r->s16[i] = cvtswsh (t, &sat);
+ }
+
+ if (sat) {
+ env->vscr |= (1 << VSCR_SAT);
+ }
+}
+
+void helper_vmhraddshs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
+{
+ int sat = 0;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(r->s16); i++) {
+ int32_t prod = a->s16[i] * b->s16[i] + 0x00004000;
+ int32_t t = (int32_t)c->s16[i] + (prod >> 15);
+ r->s16[i] = cvtswsh (t, &sat);
+ }
+
+ if (sat) {
+ env->vscr |= (1 << VSCR_SAT);
+ }
+}
+
#define VMINMAX_DO(name, compare, element) \
void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index bc1a1ff..ce25033 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6477,6 +6477,8 @@ GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
tcg_temp_free_ptr(rd); \
}
+GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
+
GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
GEN_VAFORM_PAIRED(vsel, vperm, 21)
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [PATCH 36/40] Add vmsumuh{m,s} instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (34 preceding siblings ...)
2008-12-31 3:10 ` [Qemu-devel] [PATCH 35/40] Add vmh{,r}addshs instructions Nathan Froyd
@ 2008-12-31 3:10 ` Nathan Froyd
2008-12-31 3:10 ` [Qemu-devel] [PATCH 37/40] Add vmsumsh{m,s} instructions Nathan Froyd
` (4 subsequent siblings)
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:10 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 2 ++
target-ppc/op_helper.c | 34 ++++++++++++++++++++++++++++++++++
target-ppc/translate.c | 1 +
3 files changed, 37 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 8ea8ddd..ceb7351 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -206,6 +206,8 @@ DEF_HELPER_3(vpkuwum, void, avr, avr, avr)
DEF_HELPER_3(vpkpx, void, avr, avr, avr)
DEF_HELPER_4(vmhaddshs, void, avr, avr, avr, avr)
DEF_HELPER_4(vmhraddshs, void, avr, avr, avr, avr)
+DEF_HELPER_4(vmsumuhm, void, avr, avr, avr, avr)
+DEF_HELPER_4(vmsumuhs, void, avr, avr, avr, avr)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 8c354c3..7c72a52 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2260,6 +2260,40 @@ void helper_vmsumubm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
}
}
+void helper_vmsumuhm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
+{
+ uint32_t prod[8];
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(r->u16); i++) {
+ prod[i] = a->u16[i] * b->u16[i];
+ }
+
+ VECTOR_FOR_INORDER_I(i, u32) {
+ r->u32[i] = c->u32[i] + prod[2*i] + prod[2*i+1];
+ }
+}
+
+void helper_vmsumuhs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
+{
+ uint32_t prod[8];
+ int i;
+ int sat = 0;
+
+ for (i = 0; i < ARRAY_SIZE(r->u16); i++) {
+ prod[i] = a->u16[i] * b->u16[i];
+ }
+
+ VECTOR_FOR_INORDER_I (i, s32) {
+ uint64_t t = (uint64_t)c->u32[i] + prod[2*i] + prod[2*i+1];
+ r->u32[i] = cvtuduw(t, &sat);
+ }
+
+ if (sat) {
+ env->vscr |= (1 << VSCR_SAT);
+ }
+}
+
#define VMUL_DO(name, mul_element, prod_element, evenp) \
void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index ce25033..9e0b58e 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6480,6 +6480,7 @@ GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
+GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
GEN_VAFORM_PAIRED(vsel, vperm, 21)
/*** SPE extension ***/
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [PATCH 37/40] Add vmsumsh{m,s} instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (35 preceding siblings ...)
2008-12-31 3:10 ` [Qemu-devel] [PATCH 36/40] Add vmsumuh{m,s} instructions Nathan Froyd
@ 2008-12-31 3:10 ` Nathan Froyd
2008-12-31 3:10 ` [Qemu-devel] [PATCH 38/40] Add vmladduhm instruction Nathan Froyd
` (3 subsequent siblings)
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:10 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 2 ++
target-ppc/op_helper.c | 34 ++++++++++++++++++++++++++++++++++
target-ppc/translate.c | 1 +
3 files changed, 37 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index ceb7351..b4b9521 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -208,6 +208,8 @@ DEF_HELPER_4(vmhaddshs, void, avr, avr, avr, avr)
DEF_HELPER_4(vmhraddshs, void, avr, avr, avr, avr)
DEF_HELPER_4(vmsumuhm, void, avr, avr, avr, avr)
DEF_HELPER_4(vmsumuhs, void, avr, avr, avr, avr)
+DEF_HELPER_4(vmsumshm, void, avr, avr, avr, avr)
+DEF_HELPER_4(vmsumshs, void, avr, avr, avr, avr)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 7c72a52..097153e 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2246,6 +2246,40 @@ void helper_vmsummbm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
}
}
+void helper_vmsumshm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
+{
+ int32_t prod[8];
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(r->s16); i++) {
+ prod[i] = a->s16[i] * b->s16[i];
+ }
+
+ VECTOR_FOR_INORDER_I(i, s32) {
+ r->s32[i] = c->s32[i] + prod[2*i] + prod[2*i+1];
+ }
+}
+
+void helper_vmsumshs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
+{
+ int32_t prod[8];
+ int i;
+ int sat = 0;
+
+ for (i = 0; i < ARRAY_SIZE(r->s16); i++) {
+ prod[i] = (int32_t)a->s16[i] * b->s16[i];
+ }
+
+ VECTOR_FOR_INORDER_I (i, s32) {
+ int64_t t = (int64_t)c->s32[i] + prod[2*i] + prod[2*i+1];
+ r->u32[i] = cvtsdsw(t, &sat);
+ }
+
+ if (sat) {
+ env->vscr |= (1 << VSCR_SAT);
+ }
+}
+
void helper_vmsumubm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
{
uint16_t prod[16];
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 9e0b58e..a9ab8d5 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6481,6 +6481,7 @@ GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
+GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
GEN_VAFORM_PAIRED(vsel, vperm, 21)
/*** SPE extension ***/
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [PATCH 38/40] Add vmladduhm instruction.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (36 preceding siblings ...)
2008-12-31 3:10 ` [Qemu-devel] [PATCH 37/40] Add vmsumsh{m,s} instructions Nathan Froyd
@ 2008-12-31 3:10 ` Nathan Froyd
2008-12-31 3:10 ` [Qemu-devel] [PATCH 39/40] Add {l,st}ve{b,h,w}x instructions Nathan Froyd
` (2 subsequent siblings)
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:10 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 1 +
target-ppc/op_helper.c | 11 ++++++++++-
target-ppc/translate.c | 18 ++++++++++++++++++
3 files changed, 29 insertions(+), 1 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index b4b9521..f97480e 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -210,6 +210,7 @@ DEF_HELPER_4(vmsumuhm, void, avr, avr, avr, avr)
DEF_HELPER_4(vmsumuhs, void, avr, avr, avr, avr)
DEF_HELPER_4(vmsumshm, void, avr, avr, avr, avr)
DEF_HELPER_4(vmsumshs, void, avr, avr, avr, avr)
+DEF_HELPER_4(vmladduhm, void, avr, avr, avr, avr)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 097153e..4fe6d43 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2197,12 +2197,21 @@ VMINMAX(uw, u32)
#undef VMINMAX_DO
#undef VMINMAX
+void helper_vmladduhm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(r->s16); i++) {
+ int32_t prod = a->s16[i] * b->s16[i];
+ r->s16[i] = (int16_t) (prod + c->s16[i]);
+ }
+}
+
#define VMRG_DO(name, element, highp) \
void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
ppc_avr_t result; \
int i; \
- size_t n_elems = N_ELEMS(element); \
+ size_t n_elems = ARRAY_SIZE(r->element); \
for (i = 0; i < n_elems/2; i++) { \
if (highp) { \
result.element[i*2+HI_IDX] = a->element[i]; \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index a9ab8d5..93cebcf 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6479,6 +6479,24 @@ GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
+GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC)
+{
+ TCGv_ptr ra, rb, rc, rd;
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+ ra = gen_avr_ptr(rA(ctx->opcode));
+ rb = gen_avr_ptr(rB(ctx->opcode));
+ rc = gen_avr_ptr(rC(ctx->opcode));
+ rd = gen_avr_ptr(rD(ctx->opcode));
+ gen_helper_vmladduhm(rd, ra, rb, rc);
+ tcg_temp_free_ptr(ra);
+ tcg_temp_free_ptr(rb);
+ tcg_temp_free_ptr(rc);
+ tcg_temp_free_ptr(rd);
+}
+
GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [PATCH 39/40] Add {l,st}ve{b,h,w}x instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (37 preceding siblings ...)
2008-12-31 3:10 ` [Qemu-devel] [PATCH 38/40] Add vmladduhm instruction Nathan Froyd
@ 2008-12-31 3:10 ` Nathan Froyd
2008-12-31 3:10 ` [Qemu-devel] [PATCH 40/40] Add vsumsws, vsum2sws, and vsum4{sbs, shs, ubs} instructions Nathan Froyd
2009-01-04 22:20 ` [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Aurelien Jarno
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:10 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 6 ++++++
target-ppc/op_helper.c | 40 ++++++++++++++++++++++++++++++++++++++++
target-ppc/translate.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 90 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index f97480e..1dd2cf8 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -211,6 +211,12 @@ DEF_HELPER_4(vmsumuhs, void, avr, avr, avr, avr)
DEF_HELPER_4(vmsumshm, void, avr, avr, avr, avr)
DEF_HELPER_4(vmsumshs, void, avr, avr, avr, avr)
DEF_HELPER_4(vmladduhm, void, avr, avr, avr, avr)
+DEF_HELPER_2(lvebx, void, avr, tl)
+DEF_HELPER_2(lvehx, void, avr, tl)
+DEF_HELPER_2(lvewx, void, avr, tl)
+DEF_HELPER_2(stvebx, void, avr, tl)
+DEF_HELPER_2(stvehx, void, avr, tl)
+DEF_HELPER_2(stvewx, void, avr, tl)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 4fe6d43..5c45072 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -1999,6 +1999,26 @@ SATCVT(sw, uh, int32_t, uint16_t, 0, UINT16_MAX, 1, 1)
SATCVT(sd, uw, int64_t, uint32_t, 0, UINT32_MAX, 1, 1)
#undef SATCVT
+#define LVE(name, access, swap, element) \
+ void helper_##name (ppc_avr_t *r, target_ulong addr) \
+ { \
+ size_t n_elems = ARRAY_SIZE(r->element); \
+ int adjust = HI_IDX*(n_elems-1); \
+ int sh = sizeof(r->element[0]) >> 1; \
+ int index = (addr & 0xf) >> sh; \
+ if(msr_le) { \
+ r->element[LO_IDX ? index : (adjust - index)] = swap(access(addr)); \
+ } else { \
+ r->element[LO_IDX ? index : (adjust - index)] = access(addr); \
+ } \
+ }
+#define I(x) (x)
+LVE(lvebx, ldub, I, u8)
+LVE(lvehx, lduw, bswap16, u16)
+LVE(lvewx, ldl, bswap32, u32)
+#undef I
+#undef LVE
+
void helper_lvsl (ppc_avr_t *r, target_ulong sh)
{
int i, j = (sh & 0xf);
@@ -2017,6 +2037,26 @@ void helper_lvsr (ppc_avr_t *r, target_ulong sh)
}
}
+#define STVE(name, access, swap, element) \
+ void helper_##name (ppc_avr_t *r, target_ulong addr) \
+ { \
+ size_t n_elems = ARRAY_SIZE(r->element); \
+ int adjust = HI_IDX*(n_elems-1); \
+ int sh = sizeof(r->element[0]) >> 1; \
+ int index = (addr & 0xf) >> sh; \
+ if(msr_le) { \
+ access(addr, swap(r->element[LO_IDX ? index : (adjust - index)])); \
+ } else { \
+ access(addr, r->element[LO_IDX ? index : (adjust - index)]); \
+ } \
+ }
+#define I(x) (x)
+STVE(stvebx, stb, I, u8)
+STVE(stvehx, stw, bswap16, u16)
+STVE(stvewx, stl, bswap32, u32)
+#undef I
+#undef LVE
+
void helper_vaddcuw (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
{
int i;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 93cebcf..2ec9d19 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6144,14 +6144,58 @@ GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
tcg_temp_free(EA); \
}
+#define GEN_VR_LVE(name, opc2, opc3) \
+ GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
+ { \
+ TCGv EA; \
+ TCGv_ptr rs; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ EA = tcg_temp_new(); \
+ gen_addr_reg_index(ctx, EA); \
+ rs = gen_avr_ptr(rS(ctx->opcode)); \
+ gen_helper_lve##name (rs, EA); \
+ tcg_temp_free(EA); \
+ tcg_temp_free_ptr(rs); \
+ }
+
+#define GEN_VR_STVE(name, opc2, opc3) \
+ GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
+ { \
+ TCGv EA; \
+ TCGv_ptr rs; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ EA = tcg_temp_new(); \
+ gen_addr_reg_index(ctx, EA); \
+ rs = gen_avr_ptr(rS(ctx->opcode)); \
+ gen_helper_stve##name (rs, EA); \
+ tcg_temp_free(EA); \
+ tcg_temp_free_ptr(rs); \
+ }
+
GEN_VR_LDX(lvx, 0x07, 0x03);
/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
GEN_VR_LDX(lvxl, 0x07, 0x0B);
+GEN_VR_LVE(bx, 0x07, 0x00);
+GEN_VR_LVE(hx, 0x07, 0x01);
+GEN_VR_LVE(wx, 0x07, 0x02);
+
GEN_VR_STX(svx, 0x07, 0x07);
/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
GEN_VR_STX(svxl, 0x07, 0x0F);
+GEN_VR_STVE(bx, 0x07, 0x04);
+GEN_VR_STVE(hx, 0x07, 0x05);
+GEN_VR_STVE(wx, 0x07, 0x06);
+
GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC)
{
TCGv_ptr rd;
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [PATCH 40/40] Add vsumsws, vsum2sws, and vsum4{sbs, shs, ubs} instructions.
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (38 preceding siblings ...)
2008-12-31 3:10 ` [Qemu-devel] [PATCH 39/40] Add {l,st}ve{b,h,w}x instructions Nathan Froyd
@ 2008-12-31 3:10 ` Nathan Froyd
2009-01-04 22:20 ` [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Aurelien Jarno
40 siblings, 0 replies; 68+ messages in thread
From: Nathan Froyd @ 2008-12-31 3:10 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 5 ++
target-ppc/op_helper.c | 103 ++++++++++++++++++++++++++++++++++++++++++++++++
target-ppc/translate.c | 5 ++
3 files changed, 113 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 1dd2cf8..51760a1 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -217,6 +217,11 @@ DEF_HELPER_2(lvewx, void, avr, tl)
DEF_HELPER_2(stvebx, void, avr, tl)
DEF_HELPER_2(stvehx, void, avr, tl)
DEF_HELPER_2(stvewx, void, avr, tl)
+DEF_HELPER_3(vsumsws, void, avr, avr, avr)
+DEF_HELPER_3(vsum2sws, void, avr, avr, avr)
+DEF_HELPER_3(vsum4sbs, void, avr, avr, avr)
+DEF_HELPER_3(vsum4shs, void, avr, avr, avr)
+DEF_HELPER_3(vsum4ubs, void, avr, avr, avr)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 5c45072..d72b011 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2667,6 +2667,109 @@ void helper_vsubcuw (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
}
}
+void helper_vsumsws (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ int64_t t;
+ int i, upper;
+ ppc_avr_t result;
+ int sat = 0;
+
+#if defined(WORDS_BIGENDIAN)
+ upper = ARRAY_SIZE(r->s32)-1;
+#else
+ upper = 0;
+#endif
+ t = (int64_t)b->s32[upper];
+ for (i = 0; i < ARRAY_SIZE(r->s32); i++) {
+ t += a->s32[i];
+ result.s32[i] = 0;
+ }
+ result.s32[upper] = cvtsdsw(t, &sat);
+ *r = result;
+
+ if (sat) {
+ env->vscr |= (1 << VSCR_SAT);
+ }
+}
+
+void helper_vsum2sws (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ int i, j, upper;
+ ppc_avr_t result;
+ int sat = 0;
+
+#if defined(WORDS_BIGENDIAN)
+ upper = 1;
+#else
+ upper = 0;
+#endif
+ for (i = 0; i < ARRAY_SIZE(r->u64); i++) {
+ int64_t t = (int64_t)b->s32[upper+i*2];
+ result.u64[i] = 0;
+ for (j = 0; j < ARRAY_SIZE(r->u64); j++) {
+ t += a->s32[2*i+j];
+ }
+ result.s32[upper+i*2] = cvtsdsw(t, &sat);
+ }
+
+ *r = result;
+ if (sat) {
+ env->vscr |= (1 << VSCR_SAT);
+ }
+}
+
+void helper_vsum4sbs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ int i, j;
+ int sat = 0;
+
+ for (i = 0; i < ARRAY_SIZE(r->s32); i++) {
+ int64_t t = (int64_t)b->s32[i];
+ for (j = 0; j < ARRAY_SIZE(r->s32); j++) {
+ t += a->s8[4*i+j];
+ }
+ r->s32[i] = cvtsdsw(t, &sat);
+ }
+
+ if (sat) {
+ env->vscr |= (1 << VSCR_SAT);
+ }
+}
+
+void helper_vsum4shs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ int sat = 0;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(r->s32); i++) {
+ int64_t t = (int64_t)b->s32[i];
+ t += a->s16[2*i] + a->s16[2*i+1];
+ r->s32[i] = cvtsdsw(t, &sat);
+ }
+
+ if (sat) {
+ env->vscr |= (1 << VSCR_SAT);
+ }
+}
+
+void helper_vsum4ubs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ int i, j;
+ int sat = 0;
+
+ for (i = 0; i < ARRAY_SIZE(r->u32); i++) {
+ uint64_t t = (uint64_t)b->u32[i];
+ for (j = 0; j < ARRAY_SIZE(r->u32); j++) {
+ t += a->u8[4*i+j];
+ }
+ r->u32[i] = cvtuduw(t, &sat);
+ }
+
+ if (sat) {
+ env->vscr |= (1 << VSCR_SAT);
+ }
+}
+
#if defined(WORDS_BIGENDIAN)
#define UPKHI 1
#define UPKLO 0
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 2ec9d19..593c5dd 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6377,6 +6377,11 @@ GEN_VXFORM(vpkswus, 7, 5);
GEN_VXFORM(vpkshss, 7, 6);
GEN_VXFORM(vpkswss, 7, 7);
GEN_VXFORM(vpkpx, 7, 12);
+GEN_VXFORM(vsum4ubs, 4, 24);
+GEN_VXFORM(vsum4sbs, 4, 28);
+GEN_VXFORM(vsum4shs, 4, 25);
+GEN_VXFORM(vsum2sws, 4, 26);
+GEN_VXFORM(vsumsws, 4, 30);
#define GEN_VXFORM_NOA(name, opc2, opc3) \
GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2
2008-12-31 3:09 [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Nathan Froyd
` (39 preceding siblings ...)
2008-12-31 3:10 ` [Qemu-devel] [PATCH 40/40] Add vsumsws, vsum2sws, and vsum4{sbs, shs, ubs} instructions Nathan Froyd
@ 2009-01-04 22:20 ` Aurelien Jarno
2009-01-04 22:54 ` Aurelien Jarno
40 siblings, 1 reply; 68+ messages in thread
From: Aurelien Jarno @ 2009-01-04 22:20 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Tue, Dec 30, 2008 at 07:09:42PM -0800, Nathan Froyd wrote:
> This is a follow-on to:
>
> http://lists.gnu.org/archive/html/qemu-devel/2008-12/msg01000.html
>
> as Aurelien asked me to modify the notation for defining instructions in
> target-ppc/translate.c. Since that change touched nearly every patch in
> the series, I figured I would also take the opportunity to eliminate the
> VECTOR_FOR macros that my patch used as well. I also fixed up various
> TCG errors that turned up under DEBUG_TCG.
>
> I did, however, leave the VECTOR_FOR_INORDER_I macros in place; I think
> they are the clearest way to indicate that vectors are being iterated
> over in target-endian order. Better than `#if defined(WORDS_BIGENDIAN)'
> all over the code, IMHO.
>
> As the message in:
>
> http://lists.gnu.org/archive/html/qemu-devel/2008-12/msg01106.html
>
> indicated, m{f,t}vscr seems to be broken in some way; the code looks
> correct to me, but I can't seem to puzzle out what's wrong with it. All
> other instructions have been tested against an Altivec hardware
> implementation. Except for the VSCR issue above, the simulated
> instructions perform identically to their hardware-implemented versions.
>
Thanks for your great work. I have applied all the patches of the series
except the following ones, for which I have already send comments:
- Add GEN_VXRFORM{, 1} macros for subsequent instructions.
- Add vcmpequ{b, h, w} and vcmpgt{s, u}{b, h, w} instructions.
- Add m{f,t}vscr instructions.
- Add v{add, sub}{s, u}{b, h, w}s instructions.
- Add vs{l,r} instructions.
- Add vspltis{b,h,w} instructions.
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2
2009-01-04 22:20 ` [Qemu-devel] [PATCH] target-ppc: add integer Altivec instructions, take 2 Aurelien Jarno
@ 2009-01-04 22:54 ` Aurelien Jarno
0 siblings, 0 replies; 68+ messages in thread
From: Aurelien Jarno @ 2009-01-04 22:54 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Sun, Jan 04, 2009 at 11:20:26PM +0100, Aurelien Jarno wrote:
> On Tue, Dec 30, 2008 at 07:09:42PM -0800, Nathan Froyd wrote:
> > This is a follow-on to:
> >
> > http://lists.gnu.org/archive/html/qemu-devel/2008-12/msg01000.html
> >
> > as Aurelien asked me to modify the notation for defining instructions in
> > target-ppc/translate.c. Since that change touched nearly every patch in
> > the series, I figured I would also take the opportunity to eliminate the
> > VECTOR_FOR macros that my patch used as well. I also fixed up various
> > TCG errors that turned up under DEBUG_TCG.
> >
> > I did, however, leave the VECTOR_FOR_INORDER_I macros in place; I think
> > they are the clearest way to indicate that vectors are being iterated
> > over in target-endian order. Better than `#if defined(WORDS_BIGENDIAN)'
> > all over the code, IMHO.
> >
> > As the message in:
> >
> > http://lists.gnu.org/archive/html/qemu-devel/2008-12/msg01106.html
> >
> > indicated, m{f,t}vscr seems to be broken in some way; the code looks
> > correct to me, but I can't seem to puzzle out what's wrong with it. All
> > other instructions have been tested against an Altivec hardware
> > implementation. Except for the VSCR issue above, the simulated
> > instructions perform identically to their hardware-implemented versions.
> >
>
> Thanks for your great work. I have applied all the patches of the series
> except the following ones, for which I have already send comments:
>
> - Add GEN_VXRFORM{, 1} macros for subsequent instructions.
> - Add vcmpequ{b, h, w} and vcmpgt{s, u}{b, h, w} instructions.
> - Add m{f,t}vscr instructions.
I have just committed a different patch for m{f,t}vscr instructions
(r6190). With this patch those instructions are working on my system.
Could you please confirm that it works with your testsuite?
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 68+ messages in thread