From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LHvDt-00038U-Cw for qemu-devel@nongnu.org; Wed, 31 Dec 2008 02:10:33 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LHvDs-00038F-4r for qemu-devel@nongnu.org; Wed, 31 Dec 2008 02:10:33 -0500 Received: from [199.232.76.173] (port=47618 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LHvDr-00038C-TG for qemu-devel@nongnu.org; Wed, 31 Dec 2008 02:10:31 -0500 Received: from mx20.gnu.org ([199.232.41.8]:37092) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LHvDr-0007zl-GD for qemu-devel@nongnu.org; Wed, 31 Dec 2008 02:10:31 -0500 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LHvDq-0005Oq-Hr for qemu-devel@nongnu.org; Wed, 31 Dec 2008 02:10:30 -0500 From: Nathan Froyd Date: Tue, 30 Dec 2008 19:09:49 -0800 Message-Id: <1230693022-18380-8-git-send-email-froydnj@codesourcery.com> In-Reply-To: <1230693022-18380-1-git-send-email-froydnj@codesourcery.com> References: <1230693022-18380-1-git-send-email-froydnj@codesourcery.com> Subject: [Qemu-devel] [PATCH 07/40] Add GEN_VXRFORM{, 1} macros for subsequent instructions. Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Signed-off-by: Nathan Froyd --- target-ppc/translate.c | 27 +++++++++++++++++++++++++++ 1 files changed, 27 insertions(+), 0 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 56d5c51..967d9da 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -6206,6 +6206,33 @@ GEN_VXFORM(vavgsb, 1, 20); GEN_VXFORM(vavgsh, 1, 21); GEN_VXFORM(vavgsw, 1, 22); +#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ + GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \ + { \ + TCGv_ptr ra, rb, rd; \ + TCGv_i32 result; \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + ra = gen_avr_ptr(rA(ctx->opcode)); \ + rb = gen_avr_ptr(rB(ctx->opcode)); \ + rd = gen_avr_ptr(rD(ctx->opcode)); \ + result = tcg_temp_new_i32(); \ + gen_helper_##opname (result, rd, ra, rb); \ + if (opc3 & 0x1) { \ + tcg_gen_mov_i32(cpu_crf[6], result); \ + } \ + tcg_temp_free_ptr(ra); \ + tcg_temp_free_ptr(rb); \ + tcg_temp_free_ptr(rd); \ + tcg_temp_free_i32(result); \ + } + +#define GEN_VXRFORM(name, opc2, opc3) \ + GEN_VXRFORM1(name, name, #name, opc2, opc3) \ + GEN_VXRFORM1(name, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) + /*** SPE extension ***/ /* Register moves */ -- 1.6.0.5