From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LQ6Ud-0007JE-7m for qemu-devel@nongnu.org; Thu, 22 Jan 2009 15:49:39 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LQ6Ub-0007HS-HG for qemu-devel@nongnu.org; Thu, 22 Jan 2009 15:49:38 -0500 Received: from [199.232.76.173] (port=37416 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LQ6Ub-0007HG-98 for qemu-devel@nongnu.org; Thu, 22 Jan 2009 15:49:37 -0500 Received: from mx20.gnu.org ([199.232.41.8]:41091) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LQ6Ua-0005sG-Vr for qemu-devel@nongnu.org; Thu, 22 Jan 2009 15:49:37 -0500 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LQ6Ua-0005sg-9H for qemu-devel@nongnu.org; Thu, 22 Jan 2009 15:49:36 -0500 From: Nathan Froyd Date: Thu, 22 Jan 2009 12:42:11 -0800 Message-Id: <1232656933-28425-5-git-send-email-froydnj@codesourcery.com> In-Reply-To: <1232656933-28425-1-git-send-email-froydnj@codesourcery.com> References: <1232656933-28425-1-git-send-email-froydnj@codesourcery.com> Subject: [Qemu-devel] [PATCH 4/6] Add float register read/write using XML Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Nathan Froyd Signed-off-by: Nathan Froyd --- target-ppc/translate_init.c | 32 ++++++++++++++++++++++++++++++++ 1 files changed, 32 insertions(+), 0 deletions(-) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 5ef7154..21cb894 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -9272,6 +9272,33 @@ static void dump_ppc_insns (CPUPPCState *env) } #endif +static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n) +{ + if (n < 32) { + stfq_p(mem_buf, env->fpr[n]); + return 8; + } + if (n == 32) { + /* FPSCR not implemented */ + memset(mem_buf, 0, 4); + return 4; + } + return 0; +} + +static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n) +{ + if (n < 32) { + env->fpr[n] = ldfq_p(mem_buf); + return 8; + } + if (n == 32) { + /* FPSCR not implemented */ + return 4; + } + return 0; +} + int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def) { env->msr_mask = def->msr_mask; @@ -9284,6 +9311,11 @@ int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def) if (create_ppc_opcodes(env, def) < 0) return -1; init_ppc_proc(env, def); + + if (def->insns_flags & PPC_FLOAT) { + gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg, + 33, "power-fpu.xml", 0); + } #if defined(PPC_DUMP_CPU) { const char *mmu_model, *excp_model, *bus_model; -- 1.6.0.5