From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LQ82n-0004dU-57 for qemu-devel@nongnu.org; Thu, 22 Jan 2009 17:29:01 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LQ82j-0004c6-F4 for qemu-devel@nongnu.org; Thu, 22 Jan 2009 17:29:00 -0500 Received: from [199.232.76.173] (port=57888 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LQ82j-0004bx-6c for qemu-devel@nongnu.org; Thu, 22 Jan 2009 17:28:57 -0500 Received: from mx20.gnu.org ([199.232.41.8]:43335) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LQ82i-0007Ar-V2 for qemu-devel@nongnu.org; Thu, 22 Jan 2009 17:28:57 -0500 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LQ82i-0000LQ-15 for qemu-devel@nongnu.org; Thu, 22 Jan 2009 17:28:56 -0500 From: Nathan Froyd Date: Thu, 22 Jan 2009 12:42:12 -0800 Message-Id: <1232656933-28425-6-git-send-email-froydnj@codesourcery.com> In-Reply-To: <1232656933-28425-1-git-send-email-froydnj@codesourcery.com> References: <1232656933-28425-1-git-send-email-froydnj@codesourcery.com> Subject: [Qemu-devel] [PATCH 5/6] Add Altivec register read/write using XML Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Nathan Froyd Signed-off-by: Nathan Froyd --- target-ppc/translate_init.c | 50 +++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 50 insertions(+), 0 deletions(-) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 21cb894..c90ae19 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -9299,6 +9299,52 @@ static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n) return 0; } +static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n) +{ + if (n < 32) { +#ifdef WORDS_BIGENDIAN + stq_p(mem_buf, env->avr[n].u64[0]); + stq_p(mem_buf+8, env->avr[n].u64[1]); +#else + stq_p(mem_buf, env->avr[n].u64[1]); + stq_p(mem_buf+8, env->avr[n].u64[0]); +#endif + return 16; + } + if (n == 33) { + stl_p(mem_buf, env->vscr); + return 4; + } + if (n == 34) { + stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]); + return 4; + } + return 0; +} + +static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n) +{ + if (n < 32) { +#ifdef WORDS_BIGENDIAN + env->avr[n].u64[0] = ldq_p(mem_buf); + env->avr[n].u64[1] = ldq_p(mem_buf+8); +#else + env->avr[n].u64[1] = ldq_p(mem_buf); + env->avr[n].u64[0] = ldq_p(mem_buf+8); +#endif + return 16; + } + if (n == 33) { + env->vscr = ldl_p(mem_buf); + return 4; + } + if (n == 34) { + env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf); + return 4; + } + return 0; +} + int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def) { env->msr_mask = def->msr_mask; @@ -9316,6 +9362,10 @@ int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def) gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg, 33, "power-fpu.xml", 0); } + if (def->insns_flags & PPC_ALTIVEC) { + gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg, + 34, "power-altivec.xml", 0); + } #if defined(PPC_DUMP_CPU) { const char *mmu_model, *excp_model, *bus_model; -- 1.6.0.5