From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LQ8yo-0007Dr-Sl for qemu-devel@nongnu.org; Thu, 22 Jan 2009 18:28:58 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LQ8yn-0007D6-5I for qemu-devel@nongnu.org; Thu, 22 Jan 2009 18:28:58 -0500 Received: from [199.232.76.173] (port=39438 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LQ8yn-0007D3-1j for qemu-devel@nongnu.org; Thu, 22 Jan 2009 18:28:57 -0500 Received: from mx20.gnu.org ([199.232.41.8]:44697) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LQ8ym-00055o-NU for qemu-devel@nongnu.org; Thu, 22 Jan 2009 18:28:56 -0500 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LQ8yl-000216-Nr for qemu-devel@nongnu.org; Thu, 22 Jan 2009 18:28:56 -0500 From: Nathan Froyd Date: Thu, 22 Jan 2009 12:42:13 -0800 Message-Id: <1232656933-28425-7-git-send-email-froydnj@codesourcery.com> In-Reply-To: <1232656933-28425-1-git-send-email-froydnj@codesourcery.com> References: <1232656933-28425-1-git-send-email-froydnj@codesourcery.com> Subject: [Qemu-devel] [PATCH 6/6] Add SPE register read/write using XML Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Nathan Froyd Don't read/write SPEFSCR until we figure out what to do about exceptions. Signed-off-by: Nathan Froyd --- target-ppc/translate_init.c | 50 +++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 50 insertions(+), 0 deletions(-) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index c90ae19..803b91e 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -9345,6 +9345,51 @@ static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n) return 0; } +static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n) +{ + if (n < 32) { +#if defined(TARGET_POWERPC64) + stl_p(mem_buf, env->gpr[n] >> 32); +#else + stl_p(mem_buf, env->gprh[n]); +#endif + return 4; + } + if (n == 33) { + stq_p(mem_buf, env->spe_acc); + return 8; + } + if (n == 34) { + /* SPEFSCR not implemented */ + memset(mem_buf, 0, 4); + return 4; + } + return 0; +} + +static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n) +{ + if (n < 32) { +#if defined(TARGET_POWERPC64) + target_ulong lo = (uint32_t)env->gpr[n]; + target_ulong hi = ldl_p(mem_buf) << 32; + env->gpr[n] = lo | hi; +#else + env->gprh[n] = ldl_p(mem_buf); +#endif + return 4; + } + if (n == 33) { + env->spe_acc = ldq_p(mem_buf); + return 8; + } + if (n == 34) { + /* SPEFSCR not implemented */ + return 4; + } + return 0; +} + int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def) { env->msr_mask = def->msr_mask; @@ -9366,6 +9411,11 @@ int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def) gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg, 34, "power-altivec.xml", 0); } + if ((def->insns_flags & PPC_SPE) | (def->insns_flags & PPC_SPEFPU)) { + gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg, + 34, "power-spe.xml", 0); + } + #if defined(PPC_DUMP_CPU) { const char *mmu_model, *excp_model, *bus_model; -- 1.6.0.5