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From: Alexander Graf <agraf@suse.de>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH 1/2] Implement FFXSR
Date: Tue, 27 Jan 2009 13:35:25 +0100	[thread overview]
Message-ID: <1233059726-8566-2-git-send-email-agraf@suse.de> (raw)
In-Reply-To: <1233059726-8566-1-git-send-email-agraf@suse.de>

Newer AMD CPUs have the FFXSR capability. This leaves out XMM
register in FXSAVE/FXRESTORE when in CPL=0 and 64-bit mode.

This is required for Hyper-V.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-i386/op_helper.c |   28 ++++++++++++++++++++--------
 1 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c
index 8cf3bb2..c69328a 100644
--- a/target-i386/op_helper.c
+++ b/target-i386/op_helper.c
@@ -3030,6 +3030,8 @@ void helper_wrmsr(void)
                 update_mask |= MSR_EFER_NXE;
             if (env->cpuid_ext3_features & CPUID_EXT3_SVM)
                 update_mask |= MSR_EFER_SVME;
+            if (env->cpuid_ext2_features & CPUID_EXT2_FFXSR)
+                update_mask |= MSR_EFER_FFXSR;
             cpu_load_efer(env, (env->efer & ~update_mask) |
                           (val & update_mask));
         }
@@ -4345,10 +4347,15 @@ void helper_fxsave(target_ulong ptr, int data64)
         else
             nb_xmm_regs = 8;
         addr = ptr + 0xa0;
-        for(i = 0; i < nb_xmm_regs; i++) {
-            stq(addr, env->xmm_regs[i].XMM_Q(0));
-            stq(addr + 8, env->xmm_regs[i].XMM_Q(1));
-            addr += 16;
+        /* Fast FXSAVE leaves out the XMM registers */
+        if (!(env->efer & MSR_EFER_FFXSR)
+          || (env->hflags & HF_CPL_MASK)
+          || !(env->hflags & HF_LMA_MASK)) {
+            for(i = 0; i < nb_xmm_regs; i++) {
+                stq(addr, env->xmm_regs[i].XMM_Q(0));
+                stq(addr + 8, env->xmm_regs[i].XMM_Q(1));
+                addr += 16;
+            }
         }
     }
 }
@@ -4385,10 +4392,15 @@ void helper_fxrstor(target_ulong ptr, int data64)
         else
             nb_xmm_regs = 8;
         addr = ptr + 0xa0;
-        for(i = 0; i < nb_xmm_regs; i++) {
-            env->xmm_regs[i].XMM_Q(0) = ldq(addr);
-            env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8);
-            addr += 16;
+        /* Fast FXRESTORE leaves out the XMM registers */
+        if (!(env->efer & MSR_EFER_FFXSR)
+          || (env->hflags & HF_CPL_MASK)
+          || !(env->hflags & HF_LMA_MASK)) {
+            for(i = 0; i < nb_xmm_regs; i++) {
+                env->xmm_regs[i].XMM_Q(0) = ldq(addr);
+                env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8);
+                addr += 16;
+            }
         }
     }
 }
-- 
1.6.0.2

  reply	other threads:[~2009-01-27 12:35 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-01-27 12:35 [Qemu-devel] [PATCH 0/2] Add Phenom CPU Descriptor Alexander Graf
2009-01-27 12:35 ` Alexander Graf [this message]
2009-01-27 12:35   ` [Qemu-devel] [PATCH 2/2] Add phenom CPU descriptor Alexander Graf
2009-01-27 14:37     ` Anthony Liguori
2009-01-27 15:16       ` Alexander Graf
2009-01-27 15:33       ` Laurent Vivier
2009-01-27 19:12         ` Anthony Liguori
2009-01-27 22:39           ` Paul Brook
2009-01-27 22:56             ` Paul Brook
2009-01-28 16:43               ` Jamie Lokier
2009-01-30  9:06               ` Amit Shah
2009-01-28  8:17             ` Alexander Graf
2009-02-02 17:11 ` [Qemu-devel] [PATCH 0/2] Add Phenom CPU Descriptor Anthony Liguori

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