From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LRnAF-0003Et-1M for qemu-devel@nongnu.org; Tue, 27 Jan 2009 07:35:35 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LRnAC-0003EA-Q3 for qemu-devel@nongnu.org; Tue, 27 Jan 2009 07:35:34 -0500 Received: from [199.232.76.173] (port=37929 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LRnAC-0003E6-NB for qemu-devel@nongnu.org; Tue, 27 Jan 2009 07:35:32 -0500 Received: from ns.suse.de ([195.135.220.2]:59648 helo=mx1.suse.de) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LRnAC-0002DI-5v for qemu-devel@nongnu.org; Tue, 27 Jan 2009 07:35:32 -0500 Received: from Relay1.suse.de (mail2.suse.de [195.135.221.8]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.suse.de (Postfix) with ESMTP id 33A834459C for ; Tue, 27 Jan 2009 13:35:27 +0100 (CET) From: Alexander Graf Date: Tue, 27 Jan 2009 13:35:25 +0100 Message-Id: <1233059726-8566-2-git-send-email-agraf@suse.de> In-Reply-To: <1233059726-8566-1-git-send-email-agraf@suse.de> References: <1233059726-8566-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PATCH 1/2] Implement FFXSR Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Newer AMD CPUs have the FFXSR capability. This leaves out XMM register in FXSAVE/FXRESTORE when in CPL=0 and 64-bit mode. This is required for Hyper-V. Signed-off-by: Alexander Graf --- target-i386/op_helper.c | 28 ++++++++++++++++++++-------- 1 files changed, 20 insertions(+), 8 deletions(-) diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c index 8cf3bb2..c69328a 100644 --- a/target-i386/op_helper.c +++ b/target-i386/op_helper.c @@ -3030,6 +3030,8 @@ void helper_wrmsr(void) update_mask |= MSR_EFER_NXE; if (env->cpuid_ext3_features & CPUID_EXT3_SVM) update_mask |= MSR_EFER_SVME; + if (env->cpuid_ext2_features & CPUID_EXT2_FFXSR) + update_mask |= MSR_EFER_FFXSR; cpu_load_efer(env, (env->efer & ~update_mask) | (val & update_mask)); } @@ -4345,10 +4347,15 @@ void helper_fxsave(target_ulong ptr, int data64) else nb_xmm_regs = 8; addr = ptr + 0xa0; - for(i = 0; i < nb_xmm_regs; i++) { - stq(addr, env->xmm_regs[i].XMM_Q(0)); - stq(addr + 8, env->xmm_regs[i].XMM_Q(1)); - addr += 16; + /* Fast FXSAVE leaves out the XMM registers */ + if (!(env->efer & MSR_EFER_FFXSR) + || (env->hflags & HF_CPL_MASK) + || !(env->hflags & HF_LMA_MASK)) { + for(i = 0; i < nb_xmm_regs; i++) { + stq(addr, env->xmm_regs[i].XMM_Q(0)); + stq(addr + 8, env->xmm_regs[i].XMM_Q(1)); + addr += 16; + } } } } @@ -4385,10 +4392,15 @@ void helper_fxrstor(target_ulong ptr, int data64) else nb_xmm_regs = 8; addr = ptr + 0xa0; - for(i = 0; i < nb_xmm_regs; i++) { - env->xmm_regs[i].XMM_Q(0) = ldq(addr); - env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8); - addr += 16; + /* Fast FXRESTORE leaves out the XMM registers */ + if (!(env->efer & MSR_EFER_FFXSR) + || (env->hflags & HF_CPL_MASK) + || !(env->hflags & HF_LMA_MASK)) { + for(i = 0; i < nb_xmm_regs; i++) { + env->xmm_regs[i].XMM_Q(0) = ldq(addr); + env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8); + addr += 16; + } } } } -- 1.6.0.2