From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LWIf0-0006lC-Ks for qemu-devel@nongnu.org; Sun, 08 Feb 2009 18:01:58 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LWIez-0006km-62 for qemu-devel@nongnu.org; Sun, 08 Feb 2009 18:01:58 -0500 Received: from [199.232.76.173] (port=47933 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LWIez-0006kj-0y for qemu-devel@nongnu.org; Sun, 08 Feb 2009 18:01:57 -0500 Received: from mx20.gnu.org ([199.232.41.8]:63076) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LWIey-00086m-Iy for qemu-devel@nongnu.org; Sun, 08 Feb 2009 18:01:56 -0500 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LWIex-00064i-DF for qemu-devel@nongnu.org; Sun, 08 Feb 2009 18:01:55 -0500 From: Nathan Froyd Date: Sun, 8 Feb 2009 15:01:51 -0800 Message-Id: <1234134113-13893-1-git-send-email-froydnj@codesourcery.com> Subject: [Qemu-devel] [PATCH 0/2] Model SPE-using chips more accurately Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This patch series fixes up some inconsistencies in how QEMU treated PPC chips with SPE capabilities: - no distinction between SPE single-precision and double-precision instructions; - no distinction between e500v1 chips and e500v2 chips. -Nathan