From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LeJuS-000617-2G for qemu-devel@nongnu.org; Mon, 02 Mar 2009 20:59:04 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LeJuQ-000605-La for qemu-devel@nongnu.org; Mon, 02 Mar 2009 20:59:03 -0500 Received: from [199.232.76.173] (port=58883 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LeJuQ-0005zx-91 for qemu-devel@nongnu.org; Mon, 02 Mar 2009 20:59:02 -0500 Received: from mx20.gnu.org ([199.232.41.8]:37485) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LeJuP-0004KF-Ta for qemu-devel@nongnu.org; Mon, 02 Mar 2009 20:59:02 -0500 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LeJuP-0001Q2-1d for qemu-devel@nongnu.org; Mon, 02 Mar 2009 20:59:01 -0500 From: Nathan Froyd Date: Mon, 2 Mar 2009 17:58:40 -0800 Message-Id: <1236045521-15978-2-git-send-email-froydnj@codesourcery.com> In-Reply-To: <1236045521-15978-1-git-send-email-froydnj@codesourcery.com> References: <1236045521-15978-1-git-send-email-froydnj@codesourcery.com> Subject: [Qemu-devel] [PATCH 1/2] Fix off-by-one errors for Altivec and SPE registers Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Altivec and SPE both have 34 registers in their register sets, not 35 with a missing register 32. GDB would ask for register 32 of the Altivec (resp. SPE) registers and the code would claim it had zero width. The QEMU GDB stub code would then return an E14 to GDB, which would complain about not being sure whether p packets were supported or not. Signed-off-by: Nathan Froyd --- target-ppc/translate_init.c | 16 ++++++++-------- 1 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 9127081..229bfdb 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -9368,11 +9368,11 @@ static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n) #endif return 16; } - if (n == 33) { + if (n == 32) { stl_p(mem_buf, env->vscr); return 4; } - if (n == 34) { + if (n == 33) { stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]); return 4; } @@ -9391,11 +9391,11 @@ static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n) #endif return 16; } - if (n == 33) { + if (n == 32) { env->vscr = ldl_p(mem_buf); return 4; } - if (n == 34) { + if (n == 33) { env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf); return 4; } @@ -9412,11 +9412,11 @@ static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n) #endif return 4; } - if (n == 33) { + if (n == 32) { stq_p(mem_buf, env->spe_acc); return 8; } - if (n == 34) { + if (n == 33) { /* SPEFSCR not implemented */ memset(mem_buf, 0, 4); return 4; @@ -9436,11 +9436,11 @@ static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n) #endif return 4; } - if (n == 33) { + if (n == 32) { env->spe_acc = ldq_p(mem_buf); return 8; } - if (n == 34) { + if (n == 33) { /* SPEFSCR not implemented */ return 4; } -- 1.6.0.5