From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LeK1b-00009L-4F for qemu-devel@nongnu.org; Mon, 02 Mar 2009 21:06:27 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LeK1Y-000077-Mj for qemu-devel@nongnu.org; Mon, 02 Mar 2009 21:06:25 -0500 Received: from [199.232.76.173] (port=57820 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LeK1Y-000072-HZ for qemu-devel@nongnu.org; Mon, 02 Mar 2009 21:06:24 -0500 Received: from mx20.gnu.org ([199.232.41.8]:37526) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LeK1Y-0005Mc-2i for qemu-devel@nongnu.org; Mon, 02 Mar 2009 21:06:24 -0500 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LeK1X-0001ZJ-AX for qemu-devel@nongnu.org; Mon, 02 Mar 2009 21:06:23 -0500 From: Nathan Froyd Date: Mon, 2 Mar 2009 17:58:41 -0800 Message-Id: <1236045521-15978-3-git-send-email-froydnj@codesourcery.com> In-Reply-To: <1236045521-15978-1-git-send-email-froydnj@codesourcery.com> References: <1236045521-15978-1-git-send-email-froydnj@codesourcery.com> Subject: [Qemu-devel] [PATCH 2/2] Work around QEMU GDB stub suboptimality Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org The current XML files claim, on floating point-supporting Power chips, that $f0 is register 70. This would be fine, except that register 70 for non-XML-aware GDB is FPSCR. More importantly, 70 is less than NUM_CORE_REGS (71) for Power, so a request for register 70 goes to the "core" register reading routines, rather than the floating-point register read routine we registered with gdb_register_coprocessor. Therefore, when we are talking to an XML-aware GDB, we claim that register has zero width, which causes the rest of QEMU's GDB stub to send an error back to GDB, which causes GDB to be unable to read the floating-point registers. (The problem is also present for SPE registers and occurs in a slightly different way for Altivec registers.) The best way to fix this is to have the "core register" XML files for PPC32 and PPC64 claim that there is a 4-byte register 70, which causes $f0 to be register 71, and everything works just fine from that point forward. Signed-off-by: Nathan Froyd --- gdb-xml/power-core.xml | 9 +++++++++ gdb-xml/power64-core.xml | 9 +++++++++ 2 files changed, 18 insertions(+), 0 deletions(-) diff --git a/gdb-xml/power-core.xml b/gdb-xml/power-core.xml index 0c69e8c..dae13a6 100644 --- a/gdb-xml/power-core.xml +++ b/gdb-xml/power-core.xml @@ -46,4 +46,13 @@ + + diff --git a/gdb-xml/power64-core.xml b/gdb-xml/power64-core.xml index 6cc1531..fef42e4 100644 --- a/gdb-xml/power64-core.xml +++ b/gdb-xml/power64-core.xml @@ -46,4 +46,13 @@ + + -- 1.6.0.5