From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Lfc5x-0002EV-Ip for qemu-devel@nongnu.org; Fri, 06 Mar 2009 10:36:17 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Lfc5r-0002BI-UO for qemu-devel@nongnu.org; Fri, 06 Mar 2009 10:36:13 -0500 Received: from [199.232.76.173] (port=53495 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Lfc5q-0002AR-Fe for qemu-devel@nongnu.org; Fri, 06 Mar 2009 10:36:10 -0500 Received: from ns.suse.de ([195.135.220.2]:60602 helo=mx1.suse.de) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Lfc5p-0001ag-MD for qemu-devel@nongnu.org; Fri, 06 Mar 2009 10:36:09 -0500 From: Alexander Graf Date: Fri, 6 Mar 2009 16:36:00 +0100 Message-Id: <1236353765-4484-7-git-send-email-agraf@suse.de> In-Reply-To: <1236353765-4484-6-git-send-email-agraf@suse.de> References: <1236353765-4484-1-git-send-email-agraf@suse.de> <1236353765-4484-2-git-send-email-agraf@suse.de> <1236353765-4484-3-git-send-email-agraf@suse.de> <1236353765-4484-4-git-send-email-agraf@suse.de> <1236353765-4484-5-git-send-email-agraf@suse.de> <1236353765-4484-6-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PATCH 06/11] PPC64: Enable 64bit mode on interrupts Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: blauwirbel@gmail.com, Alexander Graf Real 970s enable MSR_SF on all interrupts. The current code didn't do this until now, so let's activate it! Signed-off-by: Alexander Graf --- target-ppc/helper.c | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/target-ppc/helper.c b/target-ppc/helper.c index 0fa87dc..7fe3f8f 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -2607,7 +2607,7 @@ static always_inline void powerpc_excp (CPUState *env, new_msr |= (target_ulong)1 << MSR_CM; } } else { - if (!msr_isf) { + if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) { new_msr &= ~((target_ulong)1 << MSR_SF); vector = (uint32_t)vector; } else { @@ -2788,6 +2788,10 @@ void cpu_ppc_reset (void *opaque) ppc_tlb_invalidate_all(env); #endif env->msr = msr & env->msr_mask; +#if defined(TARGET_PPC64) + if (env->mmu_model & POWERPC_MMU_64) + env->msr |= (1ULL << MSR_SF); +#endif hreg_compute_hflags(env); env->reserve = (target_ulong)-1ULL; /* Be sure no exception or interrupt is pending */ -- 1.6.0.2