From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Lfg8q-0001PY-8T for qemu-devel@nongnu.org; Fri, 06 Mar 2009 14:55:32 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Lfg8n-0001Oh-Uw for qemu-devel@nongnu.org; Fri, 06 Mar 2009 14:55:31 -0500 Received: from [199.232.76.173] (port=35330 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Lfg8n-0001ON-Pm for qemu-devel@nongnu.org; Fri, 06 Mar 2009 14:55:29 -0500 Received: from e35.co.us.ibm.com ([32.97.110.153]:58489) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Lfg8n-0003m1-8t for qemu-devel@nongnu.org; Fri, 06 Mar 2009 14:55:29 -0500 Received: from d03relay04.boulder.ibm.com (d03relay04.boulder.ibm.com [9.17.195.106]) by e35.co.us.ibm.com (8.13.1/8.13.1) with ESMTP id n26JpMn7024686 for ; Fri, 6 Mar 2009 12:51:22 -0700 Received: from d03av02.boulder.ibm.com (d03av02.boulder.ibm.com [9.17.195.168]) by d03relay04.boulder.ibm.com (8.13.8/8.13.8/NCO v9.2) with ESMTP id n26JtMB2161882 for ; Fri, 6 Mar 2009 12:55:22 -0700 Received: from d03av02.boulder.ibm.com (loopback [127.0.0.1]) by d03av02.boulder.ibm.com (8.12.11.20060308/8.13.3) with ESMTP id n26JtLxP007152 for ; Fri, 6 Mar 2009 12:55:22 -0700 Subject: Re: [Qemu-devel] [PATCH 10/11] PPC64: Keep SLB in-CPU From: Hollis Blanchard In-Reply-To: <1236353765-4484-11-git-send-email-agraf@suse.de> References: <1236353765-4484-1-git-send-email-agraf@suse.de> <1236353765-4484-2-git-send-email-agraf@suse.de> <1236353765-4484-3-git-send-email-agraf@suse.de> <1236353765-4484-4-git-send-email-agraf@suse.de> <1236353765-4484-5-git-send-email-agraf@suse.de> <1236353765-4484-6-git-send-email-agraf@suse.de> <1236353765-4484-7-git-send-email-agraf@suse.de> <1236353765-4484-8-git-send-email-agraf@suse.de> <1236353765-4484-9-git-send-email-agraf@suse.de> <1236353765-4484-10-git-send-email-agraf@suse.de> <1236353765-4484-11-git-send-email-agraf@suse.de> Content-Type: text/plain Date: Fri, 06 Mar 2009 13:55:20 -0600 Message-Id: <1236369320.26866.55.camel@slate.austin.ibm.com> Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: blauwirbel@gmail.com, Alexander Graf On Fri, 2009-03-06 at 16:36 +0100, Alexander Graf wrote: > Real 970 CPUs have the SLB not memory backed, but inside the CPU. > This breaks bridge mode for 970 for now, but at least keeps us from > overwriting physical addresses 0x0 - 0x300, rendering our interrupt > handlers useless. > > I put in some stubs for bridge mode operation that could be enabled > easily, but for now it's safer to leave that off I guess (970fx doesn't > have bridge mode AFAIK). The original code below is absolutely crazy. The architecture never provided for hardware to write into memory like this in the first place. In other words, the ifdefed "bridge" code should be removed with prejudice. For backwards compatibility, the architecture does allow for implementations with an SLB to optionally do *lookups* in the (legacy) segment table. > diff --git a/target-ppc/helper.c b/target-ppc/helper.c > index 58b7fe2..95958d4 100644 > --- a/target-ppc/helper.c > +++ b/target-ppc/helper.c > @@ -692,14 +692,48 @@ static always_inline int find_pte (CPUState *env, mmu_ctx_t *ctx, ... > +static void slb_set_entry(CPUPPCState *env, int nr, ppc_slb_t *slb) > +{ > + ppc_slb_t *entry = &env->slb[nr]; > + > +#if 0 // XXX implement bridge mode? > + if (bridge_mode) { > + target_phys_addr_t sr_base = env->spr[SPR_ASR] + (12 * nr); > + > + stq_phys(sr_base, slb->tmp64); > + stl_phys(sr_base + 8, slb->tmp); > + } else > +#endif > + if (slb == entry) > + return; > + > + entry->tmp64 = slb->tmp64; > + entry->tmp = slb->tmp; > +} -- Hollis Blanchard IBM Linux Technology Center