From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Lg1tM-0003Yi-7r for qemu-devel@nongnu.org; Sat, 07 Mar 2009 14:09:00 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Lg1tK-0003Wv-Dt for qemu-devel@nongnu.org; Sat, 07 Mar 2009 14:08:59 -0500 Received: from [199.232.76.173] (port=57957 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Lg1tK-0003Wf-Am for qemu-devel@nongnu.org; Sat, 07 Mar 2009 14:08:58 -0500 Received: from mx2.suse.de ([195.135.220.15]:51028) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Lg1tJ-0002nn-NO for qemu-devel@nongnu.org; Sat, 07 Mar 2009 14:08:58 -0500 From: Alexander Graf Date: Sat, 7 Mar 2009 20:08:48 +0100 Message-Id: <1236452932-31622-8-git-send-email-agraf@suse.de> In-Reply-To: <1236452932-31622-7-git-send-email-agraf@suse.de> References: <1236452932-31622-1-git-send-email-agraf@suse.de> <1236452932-31622-2-git-send-email-agraf@suse.de> <1236452932-31622-3-git-send-email-agraf@suse.de> <1236452932-31622-4-git-send-email-agraf@suse.de> <1236452932-31622-5-git-send-email-agraf@suse.de> <1236452932-31622-6-git-send-email-agraf@suse.de> <1236452932-31622-7-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PATCH 07/11] PPC64: Implement mtfsf.L encoding Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: blauwirbel@gmail.com, Alexander Graf Mtfsf can have the L bit set, so all the register contents get stored in FPSCR. Linux uses it, so let's implement it. Signed-off-by: Alexander Graf --- target-ppc/translate.c | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index b5de33b..1ea3830 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -2416,9 +2416,10 @@ GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT) } /* mtfsf */ -GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT) +GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT) { TCGv_i32 t0; + int L = ctx->opcode & 0x02000000; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); @@ -2427,7 +2428,10 @@ GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT) /* NIP cannot be restored if the memory exception comes from an helper */ gen_update_nip(ctx, ctx->nip - 4); gen_reset_fpstatus(); - t0 = tcg_const_i32(FM(ctx->opcode)); + if (L) + t0 = tcg_const_i32(0xff); + else + t0 = tcg_const_i32(FM(ctx->opcode)); gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0); tcg_temp_free_i32(t0); if (unlikely(Rc(ctx->opcode) != 0)) { -- 1.6.0.2