From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Li8GF-0006UO-1i for qemu-devel@nongnu.org; Fri, 13 Mar 2009 10:21:19 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Li8G6-0006Lm-Tp for qemu-devel@nongnu.org; Fri, 13 Mar 2009 10:21:16 -0400 Received: from [199.232.76.173] (port=50627 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Li8G5-0006LN-Ut for qemu-devel@nongnu.org; Fri, 13 Mar 2009 10:21:10 -0400 Received: from mel.act-europe.fr ([212.99.106.210]:53566) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Li8G4-0002Uc-TO for qemu-devel@nongnu.org; Fri, 13 Mar 2009 10:21:09 -0400 From: Tristan Gingold Date: Fri, 13 Mar 2009 15:20:36 +0100 Message-Id: <1236954043-91856-18-git-send-email-gingold@adacore.com> In-Reply-To: <1236954043-91856-17-git-send-email-gingold@adacore.com> References: <1236954043-91856-1-git-send-email-gingold@adacore.com> <1236954043-91856-2-git-send-email-gingold@adacore.com> <1236954043-91856-3-git-send-email-gingold@adacore.com> <1236954043-91856-4-git-send-email-gingold@adacore.com> <1236954043-91856-5-git-send-email-gingold@adacore.com> <1236954043-91856-6-git-send-email-gingold@adacore.com> <1236954043-91856-7-git-send-email-gingold@adacore.com> <1236954043-91856-8-git-send-email-gingold@adacore.com> <1236954043-91856-9-git-send-email-gingold@adacore.com> <1236954043-91856-10-git-send-email-gingold@adacore.com> <1236954043-91856-11-git-send-email-gingold@adacore.com> <1236954043-91856-12-git-send-email-gingold@adacore.com> <1236954043-91856-13-git-send-email-gingold@adacore.com> <1236954043-91856-14-git-send-email-gingold@adacore.com> <1236954043-91856-15-git-send-email-gingold@adacore.com> <1236954043-91856-16-git-send-email-gingold@adacore.com> <1236954043-91856-17-git-send-email-gingold@adacore.com> Subject: [Qemu-devel] [PATCH 17/24] Add instruction name in comments for hw_ld opcode. Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Tristan Gingold Make code slightly easier to read. Also unused hw_ld opcodes now generate an invalid opc fault. Signed-off-by: Tristan Gingold --- target-alpha/translate.c | 40 ++++++++++++++++++++-------------------- 1 files changed, 20 insertions(+), 20 deletions(-) diff --git a/target-alpha/translate.c b/target-alpha/translate.c index df50d1c..51a628c 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -1793,62 +1793,62 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) tcg_gen_movi_i64(addr, disp12); switch ((insn >> 12) & 0xF) { case 0x0: - /* Longword physical access */ + /* Longword physical access (hw_ldl/p) */ gen_helper_ldl_raw(cpu_ir[ra], addr); break; case 0x1: - /* Quadword physical access */ + /* Quadword physical access (hw_ldq/p) */ gen_helper_ldq_raw(cpu_ir[ra], addr); break; case 0x2: - /* Longword physical access with lock */ + /* Longword physical access with lock (hw_ldl_l/p) */ gen_helper_ldl_l_raw(cpu_ir[ra], addr); break; case 0x3: - /* Quadword physical access with lock */ + /* Quadword physical access with lock (hw_ldq_l/p) */ gen_helper_ldq_l_raw(cpu_ir[ra], addr); break; case 0x4: - /* Longword virtual PTE fetch */ - gen_helper_ldl_kernel(cpu_ir[ra], addr); + /* Longword virtual PTE fetch (hw_ldl/v) */ + tcg_gen_qemu_ld32s(cpu_ir[ra], addr, 0); break; case 0x5: - /* Quadword virtual PTE fetch */ - gen_helper_ldq_kernel(cpu_ir[ra], addr); + /* Quadword virtual PTE fetch (hw_ldq/v) */ + tcg_gen_qemu_ld64(cpu_ir[ra], addr, 0); break; case 0x6: /* Incpu_ir[ra]id */ - goto incpu_ir[ra]id_opc; + goto invalid_opc; case 0x7: /* Incpu_ir[ra]id */ - goto incpu_ir[ra]id_opc; + goto invalid_opc; case 0x8: - /* Longword virtual access */ + /* Longword virtual access (hw_ldl) */ gen_helper_st_virt_to_phys(addr, addr); gen_helper_ldl_raw(cpu_ir[ra], addr); break; case 0x9: - /* Quadword virtual access */ + /* Quadword virtual access (hw_ldq) */ gen_helper_st_virt_to_phys(addr, addr); gen_helper_ldq_raw(cpu_ir[ra], addr); break; case 0xA: - /* Longword virtual access with protection check */ - tcg_gen_qemu_ld32s(cpu_ir[ra], addr, ctx->flags); + /* Longword virtual access with protection check (hw_ldl/w) */ + tcg_gen_qemu_ld32s(cpu_ir[ra], addr, 0); break; case 0xB: - /* Quadword virtual access with protection check */ - tcg_gen_qemu_ld64(cpu_ir[ra], addr, ctx->flags); + /* Quadword virtual access with protection check (hw_ldq/w) */ + tcg_gen_qemu_ld64(cpu_ir[ra], addr, 0); break; case 0xC: - /* Longword virtual access with altenate access mode */ + /* Longword virtual access with alt access mode (hw_ldl/a)*/ gen_helper_set_alt_mode(); gen_helper_st_virt_to_phys(addr, addr); gen_helper_ldl_raw(cpu_ir[ra], addr); gen_helper_restore_mode(); break; case 0xD: - /* Quadword virtual access with altenate access mode */ + /* Quadword virtual access with alt access mode (hw_ldq/a) */ gen_helper_set_alt_mode(); gen_helper_st_virt_to_phys(addr, addr); gen_helper_ldq_raw(cpu_ir[ra], addr); @@ -1856,7 +1856,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0xE: /* Longword virtual access with alternate access mode and - * protection checks + * protection checks (hw_ldl/wa) */ gen_helper_set_alt_mode(); gen_helper_ldl_data(cpu_ir[ra], addr); @@ -1864,7 +1864,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0xF: /* Quadword virtual access with alternate access mode and - * protection checks + * protection checks (hw_ldq/wa) */ gen_helper_set_alt_mode(); gen_helper_ldq_data(cpu_ir[ra], addr); -- 1.6.2